公开(公告)号：US11070754B1

公开(公告)日：2021-07-20

申请号：US16828423

申请日：2020-03-24

Applicant: STMicroelectronics Asia Pacific Pte Ltd. ,  STMicroelectronics (Alps) SAS

Inventor： Hongliang Zhang ,  Lookah Chua ,  Celine Mas ,  Wai Yin Hnin

IPC: H04N5/225 ,  H04N5/359 ,  H04N5/374

Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

公开(公告)号：US20210157668A1

公开(公告)日：2021-05-27

申请号：US16953993

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Nicolas Anquet ,  Dragos Davidescu

IPC: G06F11/07 ,  G06F13/42 ,  G06F21/44

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

公开(公告)号：US20200336138A1

公开(公告)日：2020-10-22

申请号：US16849020

申请日：2020-04-15

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

Inventor： Giovanni Luca TORRISI ,  Domenico aka Massimo PORTO ,  Christophe ROUSSEL

IPC: H03K17/00 ,  H02P7/03

Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

公开(公告)号：US20200210569A1

公开(公告)日：2020-07-02

申请号：US16728946

申请日：2019-12-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Diana Moisuc ,  Christophe Laurencin

IPC: G06F21/55 ,  H01L23/00 ,  H02H1/00

Abstract: In an embodiment, an electronic circuit includes a plurality of protective nodes. Each protective node includes at least one monitoring circuit for processing information representative of a detection of a disturbance based on a detection circuit; and at least one reaction circuit for implementing a countermeasure controlled by the monitoring circuit.

公开(公告)号：US20200081776A1

公开(公告)日：2020-03-12

申请号：US16562025

申请日：2019-09-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gerald BRIAT ,  Antoine DE-MUYNCK ,  Alessandro BASTONI ,  Stephane MARMEY

IPC: G06F11/10 ,  G11C17/00

Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.

公开(公告)号：US10534389B2

公开(公告)日：2020-01-14

申请号：US16130706

申请日：2018-09-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Kuno Lenz

IPC: G05F1/575 ,  H02M3/156 ,  H02M3/158

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

公开(公告)号：US10514749B2

公开(公告)日：2019-12-24

申请号：US15467614

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Silvia Brini ,  Chittoor Parthasarathy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32 ,  G06F15/78 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.

公开(公告)号：US20190319540A1

公开(公告)日：2019-10-17

申请号：US16385214

申请日：2019-04-16

Applicant: STMicroelectronics (Alps) SAS

Inventor： Patrik Arno

IPC: H02M3/158

Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.

公开(公告)号：US20190191536A1

公开(公告)日：2019-06-20

申请号：US16285615

申请日：2019-02-26

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Philippe SIRITO-OLIVIER ,  Giovanni Luca TORRISI ,  Manuel GAERTNER ,  Fritz BURKHARDT

IPC: H05B39/02 ,  H05B33/08 ,  B60Q3/80 ,  B60Q1/00 ,  H05B39/04

CPC classification number: H05B39/02 ,  B60Q1/00 ,  B60Q3/80 ,  H05B33/0806 ,  H05B33/0815 ,  H05B39/047

Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.

公开(公告)号：US10326482B2

公开(公告)日：2019-06-18

申请号：US16003623

申请日：2018-06-08

Applicant: STMicroelectronics (Alps) SAS

Inventor： Herve Jacob

IPC: H04K1/02 ,  H04B1/04 ,  H03F1/22 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45

Abstract: A transmission chain receives an incident signal to be transmitted having a first power and a first bandwidth. A first modulator frequency shifts a first signal derived from the incident signal to generate a first shifted signal at a modulation output. A power amplifier coupled to the modulation output amplifies an intermediate signal to generate an amplified output signal. A predistortion-signal-generating circuit generates, from the incident signal and from the amplified output signal in a second bandwidth that is larger than the first bandwidth, a predistortion signal having a second power lower than the first power. A second modulator frequency shifts a second signal derived from the predistortion signal to generate a second shifted signal for combination with the first shifted signal at said modulation output to produce the intermediate signal.