公开(公告)号：EP3425551A1

公开(公告)日：2019-01-09

申请号：EP18178475.2

申请日：2018-06-19

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  BERTONI, Guido Marco ,  ORLANDO, William ,  VITTIMANI, Roberta

IPC: G06F21/72 ,  G06F21/60 ,  G06F21/76

Abstract: A processing system (10a) is described. The processing system (10a) comprises a first processing unit (102a), a second processing unit (106b) and cryptographic coprocessor (106c).
Specifically, the cryptographic coprocessor (106c) comprises:
- a key storage memory (1064) for storing at least one cryptographic key,
- a first interface (1068) configured to receive source data to be processed directly from the first processing unit (102a),
- a hardware crypto engine (1066) configured to process the source data as a function of at least one cryptographic key stored in the key storage memory (1064),
- a second interface (1060) configured to receive a first cryptographic key (CK) directly from the second processing unit (106b), and
- a hardware key management circuit (1074) configured to store the first cryptographic key (CK) in the key storage memory (1064).

公开(公告)号：EP3413195A1

公开(公告)日：2018-12-12

申请号：EP18173959.0

申请日：2018-05-24

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Roberto

IPC: G06F9/445

Abstract: A processing system is described. The processing system comprises a processing unit (102) and at least one configuration data client (112), each configuration data client (112) comprising a register, wherein each configuration data client (112) is configured to receive configuration data (CD) and store the configuration data (CD) received in the respective register. At least one hardware block is configured to change operation as a function of the configuration data (CD) stored in the registers of the at least one configuration data client (112). Specifically, a non-volatile memory (104) comprises the configuration data (CD), and a hardware configuration module (108) is configured to read the configuration data (CD) from the non-volatile memory (104) and transmit the configuration data (CD) to the at least one configuration data client (112).
Specifically, the hardware configuration module (108) is configured to:
- receive a command (CMD) from the processing unit (102), wherein the command (CMD) comprises an access request to the configuration data stored in the register of one of the at least one configuration data client (112); and
- selectively execute the access request.

公开(公告)号：EP2652671A2

公开(公告)日：2013-10-23

申请号：EP11796992.3

申请日：2011-12-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： CHARLES, Alexandre ,  BÖHLER, Jürgen ,  MEZIACHE, Thierry ,  RIZZO, Pierre

IPC: G06K7/00 ,  G06K7/10 ,  H04W88/06

CPC classification number: H04W4/80 ,  G06K7/0008 ,  G06K7/10237 ,  G06K7/10247 ,  H04B5/0031

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

公开(公告)号：EP2590107A1

公开(公告)日：2013-05-08

申请号：EP11306417.4

申请日：2011-11-03

Applicant: STMicroelectronics Application GmbH

Inventor： Boehler, Juergen

IPC: G06K7/00

CPC classification number: G06K7/10237

Abstract: The NFC controller analyzes (51) incoming SELECT by DF name commands, and decides according a predefined DF name table to which secure element the actual SELECT command and all following commands shall be sent for processing.

Abstract translation: NFC控制器分析（51）由DF名称命令传入SELECT，并决定gemäß预定的DF名称表，以确保哪个元素的实际SELECT命令和接下来的所有命令将用于处理被发送。

公开(公告)号：EP4187415A1

公开(公告)日：2023-05-31

申请号：EP22205161.7

申请日：2022-11-02

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： ZARGAR, Asif Rashid ,  GROSSIER, Nicolas Bernard ,  JAIN, Charul ,  COLOMBO, Roberto

IPC: G06F21/44 ,  G06F21/55 ,  G06F21/76 ,  G06F21/79 ,  G06F21/85

Abstract: A processing system (10a) is described. The processing system (10a) comprises a plurality of storage elements (113), wherein each storage element (113) is configured to receive a write request comprising a data bit (DATA) and store the received data bit (DATA) to a latch or flip-flop (1122). A hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation as a function of the logic level stored to the latch or flip-flop (1122) of a first storage element (113) of the plurality of storage elements (113). A non-volatile memory (104; 126) is configured to store data bits (CD, LCD) for the plurality of storage elements (113) and a hardware configuration circuit (108) is configured to read the data bits from the non-volatile memory (104; 126) and generate write requests in order to store the data bits to the storage elements (113).
Specifically, the hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation also as a function of the first tamper signal (TAMP). For this purpose, the first storage element (113) comprises a further latch or flip-flop (1124) and is configured to store, in response to the write request, the inverted version (1126) of the received data bit to the further latch or flip-flop (1124). The first storage element (113) comprises also a combinational logic circuit (1128) configured to compare the logic level stored to the latch or flip-flop (1122) of the first storage element (113) with the logic level stored to the further latch or flip-flop (1122) of the first storage element (113). The combinational logic circuit (1128) is configured to de-assert a first tamper signal (TAMP) associated with the first storage element (113) when the logic levels are different, and assert the first tamper signal (TAMP) when the logic levels are the same.

公开(公告)号：EP4152171A1

公开(公告)日：2023-03-22

申请号：EP22206499.0

申请日：2021-03-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： NANDLINGER, Rolf ,  OLEXA, Radek

IPC: G06F13/40

Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

公开(公告)号：EP3944457A1

公开(公告)日：2022-01-26

申请号：EP21185551.5

申请日：2021-07-14

Applicant: STMicroelectronics Application GmbH

Inventor： EKLER, Markus

IPC: H02J7/00 ,  H01M10/48 ,  H03M7/30 ,  B60L58/10 ,  H01M10/42

Abstract: A processing system (44a) configured to monitor the cell voltages of a given number (n) of cells of a rechargeable battery is described. The processing system (44a) comprises terminals (CP 0 ..CP n ) configured to be connected to the cells in order to receive the cell voltages, at least one analog to digital converter (448) is configured to generate digital samples of the cell voltages. The processing system (44a) comprises also a digital processing circuit (444a), a serial communication interface (440) and a transmission queue (452) used to interface the digital processing circuit (444a) with the serial communication interface (440), whereby the serial communication interface (440) and the digital processing circuit (444a) may operate in parallel. Specifically, the digital processing circuit (444a) is configured to synchronously acquire a given number (k) of digital samples (S 1,1 ..S n,k ) of each of the given number (n) of cell voltages and store the acquired digital samples (S 1,1 ..S n,k ) to a memory (DATA). Next, the digital processing circuit (444a) encodes the digital samples (S 1,1 ..S n,k ) stored to the memory (DATA) via a data compression module (450), thereby generating encoded data, and stores the encoded data to the transmission queue (452).
For example, the data compression module (450) may be configured to generate the encoded data by means of a dynamic range reduction operation (2004), wherein the data compression module (450) subtracts a given offset ( OFF ) from each digital sample (S 1,1 ..S n,k ), thereby generating values indicative of the dynamic variation of each sample with respect to the offset ( OFF ) , and removes a given number of most significant bits from each values. Preferably the given offset ( OFF ) is programmable.

公开(公告)号：EP3736657A1

公开(公告)日：2020-11-11

申请号：EP20171289.0

申请日：2020-04-24

Applicant: STMicroelectronics Application GmbH

Inventor： NANDLINGER, Mr. Rolf

IPC: G06F1/04 ,  H04L12/40

Abstract: A processing system is described. The processing system comprises a digital processing unit (102) programmable as a function of a firmware stored to a non-volatile memory and a resource (ADC, IF1, IF2) connected to the digital processing unit (102) via a communication system (108).
The processing system comprises also a time reference circuit (122) comprising a first digital counter circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count, and a time base distribution circuit configured to generate a time base signal ( TBI0..TBIn ) by selecting a subset of the bits of the system time signal, wherein the time base signal ( TBI0..TBIn ) is provided to the resource (ADC, IF1, IF2).
Specifically, the resource (ADC, IF1, IF2) is configured to detect a given event, store the time base signal ( TBI0 .. TBIn ) to a register (REG1..REG3) in response to the event, and signal the event to the digital processing unit (102). Conversely, the digital processing unit (102) is adapted to, in response to the event having been signaled by the resource (ADC, IF1, IF2), read via the communication system (108) the time base signal ( TBI0 .. TBIn ) from the register (REG1..REG3).

公开(公告)号：EP3599574A1

公开(公告)日：2020-01-29

申请号：EP18186154.3

申请日：2018-07-27

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics Application GmbH

Inventor： OUREDNIK, Petr ,  GOURDOU, Yvon

IPC: G06K19/077 ,  H01Q1/22 ,  H04B5/00

Abstract: The present disclosure relates to an antenna (6) comprising two planar coils (62, 64) mechanically disposed face to face and electrically connected in series.

公开(公告)号：EP3534261A1

公开(公告)日：2019-09-04

申请号：EP19159293.0

申请日：2019-02-26

Applicant: STMicroelectronics Application GmbH

Inventor： COLOMBO, Mr. Roberto

IPC: G06F11/07 ,  G06F11/10

Abstract: A processing system (10a) is described. The processing system (10a) comprises a plurality of circuits (102, 104, 106) configured to generate a plurality of error signals ( ERR ) and a plurality of error pads (EP). A fault collection circuit (108) is configured to receive at input the error signals ( ERR ) and generate a respective combined error signal ( ET ) for each of said error pads (EP). Specifically, the fault collection circuit (108) comprises a combinational logic circuit configured to generate the combined error signal ( ET ) by selectively routing the error signals ( ERR ) to the error pads (EP) as a function of a set of configuring bits.