11.
    发明专利
    未知

    公开(公告)号:DE60129945D1

    公开(公告)日:2007-09-27

    申请号:DE60129945

    申请日:2001-03-23

    Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between good and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

    SEQUENCE DETECTION
    14.
    发明专利

    公开(公告)号:AU2003239364A1

    公开(公告)日:2003-11-17

    申请号:AU2003239364

    申请日:2003-05-05

    Abstract: A system and method are disclosed for recovering a current data symbol that is part of a sequence of data symbols from a received signal. Recovering the current data symbol includes determining a set of candidate current data symbols from a set of possible current data symbols wherein the set of candidate current data symbols is a subset of the possible current data symbols that does not include all of the possible current data symbols; determining a set of candidate data symbol sequences wherein each candidate data symbol sequence includes one of the candidate current data symbols; and selecting a recovered data symbol sequence that matches the received signal from the set of candidate data symbol sequences.

    Method and system for detecting false packets in wireless communications systems

    公开(公告)号:AU2002341836A1

    公开(公告)日:2003-04-07

    申请号:AU2002341836

    申请日:2002-09-24

    Abstract: Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal values for predetermined bits in a plurality of fields. Notably, these legal values are set by a networking standard. A parity check may check may be performed in addition to checking for predetermined bits in other fields. A user interface can be used to determine the predetermined bit pattern.

    Planar high-frequency antenna
    18.
    发明专利

    公开(公告)号:AU2002316077A1

    公开(公告)日:2002-11-18

    申请号:AU2002316077

    申请日:2002-05-07

    Abstract: The present invention provides a planar antenna having a scalable multi-dipole structure for receiving, and transmitting high-frequency signals, including a plurality of opposing layers of conducting strips disposed upon either side of an insulating (dielectric) substrate. The dipoles are bifurcated between sides of a substrate on which the dipoles are disposed. A feed line is balanced to a co-axial cable and feeds one half of the bifurcated dipoles, and an independent feed line is connected to the other half of the bifurcated dipoles. Sets of the dipoles are arranged symmetrically around a center axis of the feed lines. The sets of dipoles are in series with other sets of dipoles. The antenna is ideally suited for operation in the 5.15-5.35 GHz RF band.

    Key caching system
    19.
    发明专利

    公开(公告)号:AU9089501A

    公开(公告)日:2002-03-26

    申请号:AU9089501

    申请日:2001-09-14

    Abstract: A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieved from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

    Hardware mac
    20.
    发明专利

    公开(公告)号:AU8908401A

    公开(公告)日:2002-03-26

    申请号:AU8908401

    申请日:2001-09-14

    Abstract: A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.

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