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公开(公告)号:DE60129945D1
公开(公告)日:2007-09-27
申请号:DE60129945
申请日:2001-03-23
Applicant: ATHEROS COMM INC
Inventor: TEHRANI ARDAVAN M , GILBERT JEFFREY M , MCFARLAND WILLIAM J , THON LARS E , WANG YI-HSIU , THOMSON JOHN S , HUSTED PAUL J
Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between good and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.
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公开(公告)号:IL147916A
公开(公告)日:2007-06-03
申请号:IL14791602
申请日:2002-01-30
Applicant: ATHEROS COMM INC
Abstract: The present invention provides an apparatus and method for optimizing power in order to increase capacity. Rather than having any terminal device limited to a specific maximum data rate, instead the terminal device data rate is limited by the power being used, such that the data rate can vary according to the distance that the terminal device is from the intended receiver.
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公开(公告)号:AU2003301187A1
公开(公告)日:2004-07-29
申请号:AU2003301187
申请日:2003-12-19
Applicant: ATHEROS COMM INC
Inventor: LI SHEUNG L
IPC: H04L12/28 , H04L12/56 , H04W12/12 , G06F15/177
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公开(公告)号:AU2003239364A1
公开(公告)日:2003-11-17
申请号:AU2003239364
申请日:2003-05-05
Applicant: ATHEROS COMM INC
Inventor: ZENG CHAOHUANG STEVE
IPC: H04L25/03
Abstract: A system and method are disclosed for recovering a current data symbol that is part of a sequence of data symbols from a received signal. Recovering the current data symbol includes determining a set of candidate current data symbols from a set of possible current data symbols wherein the set of candidate current data symbols is a subset of the possible current data symbols that does not include all of the possible current data symbols; determining a set of candidate data symbol sequences wherein each candidate data symbol sequence includes one of the candidate current data symbols; and selecting a recovered data symbol sequence that matches the received signal from the set of candidate data symbol sequences.
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公开(公告)号:AU2002341836A1
公开(公告)日:2003-04-07
申请号:AU2002341836
申请日:2002-09-24
Applicant: ATHEROS COMM INC
Inventor: MCFARLAND WILLIAM J , THOMSON JOHN S
Abstract: Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal values for predetermined bits in a plurality of fields. Notably, these legal values are set by a networking standard. A parity check may check may be performed in addition to checking for predetermined bits in other fields. A user interface can be used to determine the predetermined bit pattern.
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16.
公开(公告)号:AU2002327681A1
公开(公告)日:2003-04-07
申请号:AU2002327681
申请日:2002-09-19
Applicant: ATHEROS COMM INC
Inventor: DAVIDSON ANDREW M , NG TAO FEI SAMUEL , MCFARLAND WILLIAM
Abstract: Systems and methods to adapt the rate at which acknowledgements are transmitted between nodes in a wireless communication system are presented. The systems and methods enable an acknowledgement based wireless communication system to extend its range and capacity by adapting a rate at which acknowledgement packets are transmitted between nodes to match the available transmit power of the acknowledge transmitting node and the propagation environment of the wireless communication system.
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公开(公告)号:AU2002327014A1
公开(公告)日:2003-04-07
申请号:AU2002327014
申请日:2002-09-19
Applicant: ATHEROS COMM INC
Inventor: TEHRANI ARDAVAN MALEKI , BAAS BEVAN M , MENG TERESA H , MCFARLAND WILLIAM , GILBERT JEFFREY M
Abstract: A circular filtering system that prevents the problem of inter-symbol interference. The circular filtering system utilizes a buffer memory to store samples of a given symbol and provide only these samples to a linear filter such that the output of the filter, for any given symbol is formed by filtering only samples of that input symbol. Each symbol being filtered independent of other symbols hence eliminating inter-symbol interference caused by filtering. Where symbols are tolerant to a fixed phase shift for each symbol, the circular filtering system can be simplified by reducing the size of the buffer and introducing a multiplexer.
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公开(公告)号:AU2002316077A1
公开(公告)日:2002-11-18
申请号:AU2002316077
申请日:2002-05-07
Applicant: ATHEROS COMM INC
Inventor: LABARIC JOVAN E , SHOR ARIE
Abstract: The present invention provides a planar antenna having a scalable multi-dipole structure for receiving, and transmitting high-frequency signals, including a plurality of opposing layers of conducting strips disposed upon either side of an insulating (dielectric) substrate. The dipoles are bifurcated between sides of a substrate on which the dipoles are disposed. A feed line is balanced to a co-axial cable and feeds one half of the bifurcated dipoles, and an independent feed line is connected to the other half of the bifurcated dipoles. Sets of the dipoles are arranged symmetrically around a center axis of the feed lines. The sets of dipoles are in series with other sets of dipoles. The antenna is ideally suited for operation in the 5.15-5.35 GHz RF band.
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公开(公告)号:AU9089501A
公开(公告)日:2002-03-26
申请号:AU9089501
申请日:2001-09-14
Applicant: ATHEROS COMM INC
Inventor: KUSKIN JEFFREY SCOTT , NG TAO-FEI SAMUEL , DHAMDHERE DEEPAK PRABHAKAR , CAIN FIONA J , DAVIDSON ANDREW M
Abstract: A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieved from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.
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公开(公告)号:AU8908401A
公开(公告)日:2002-03-26
申请号:AU8908401
申请日:2001-09-14
Applicant: ATHEROS COMM INC
Inventor: KUSKIN JEFFREY SCOTT , NG TAO-FEI SAMUEL , DAVIDSON ANDREW M
Abstract: A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.
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