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    11.
    发明专利
    未知

    公开(公告)号：DE10158706B4

    公开(公告)日：2007-06-21

    申请号：DE10158706

    申请日：2001-11-29

    Applicant: ELPIDA MEMORY INC

    Inventor： NISSA MITSUO

    IPC: H01L29/78 ,  H01L21/265 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

    Abstract: A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).

    13.
    发明专利
    未知

    公开(公告)号：DE102004048652A1

    公开(公告)日：2005-06-30

    申请号：DE102004048652

    申请日：2004-10-06

    Applicant: ELPIDA MEMORY INC

    Inventor： KOSHIKAWA YASUJI

    IPC: G11C29/04 ,  G11C11/406 ,  G11C29/00

    Abstract: At first, failed cells are repaired using row redundancy or column redundancy as done in the past and then, for the remaining failed cells that cannot be repaired by row or column redundancy, by increasing the number of refreshes greater than that of normal cells, it is possible to repair more failed cells.

    15.
    发明专利
    未知

    公开(公告)号：DE69915158T2

    公开(公告)日：2005-04-07

    申请号：DE69915158

    申请日：1999-04-22

    Applicant: ELPIDA MEMORY INC

    Inventor： NOBUTOKI TOMOKO ,  MINE KOUJI

    IPC: G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C8/10 ,  G11C11/401 ,  H01L27/10 ,  G11C8/00

    Abstract: It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer. Data amplifiers combined with the memory cell arrays A, B, C and d respectively amplify the data read from the memory cells in the memory cell arrays A, B, C and D. The circuit blocks situated on both the side ends of a semiconductor chip respectively output activation signals for activating the data amplifiers combined with the memory cell arrays A, B, C and D. The data amplifier-activation signals outputted from the circuit blocks on the left side end are respectively inputted to the delay circuits DL1 and DL2.

    19.
    发明专利
    未知

    公开(公告)号：DE10239515A1

    公开(公告)日：2003-05-22

    申请号：DE10239515

    申请日：2002-08-28

    Applicant: ELPIDA MEMORY INC

    Inventor： HASHIMOTO TAKESHI ,  ITO YUTAKA

    IPC: G11C11/401 ,  G11C11/407 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4074

    Abstract: In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

    20.
    发明专利
    未知

    公开(公告)号：DE10233865A1

    公开(公告)日：2003-03-20

    申请号：DE10233865

    申请日：2002-07-25

    Applicant: ELPIDA MEMORY INC

    Inventor： SHIBATA KAYOKO ,  NISHIO YOJI

    IPC: H01L23/538 ,  G06F1/10 ,  G06F9/26 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C5/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/406 ,  G11C11/407 ,  H01L23/34

    Abstract: A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

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