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42 records (took 0.022 seconds)

    12.
    发明专利
    未知

    公开(公告)号：DE602007001415D1

    公开(公告)日：2009-08-13

    申请号：DE602007001415

    申请日：2007-05-15

    Applicant: ST MICROELECTRONICS PVT LTD

    Inventor： CHAWLA NITIN

    IPC: H03C3/09 ,  H03B29/00 ,  H03L7/197 ,  H04B1/69

    Abstract: The present invention provides a spread spectrum clock generation system, comprising a digitally controlled Phase Locked Loop (PLL), and a Digital Frequency Profile Generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required Noise Transfer Function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band Signal-to-Noise-Ratio (SNR) at the cost of higher out-of-band noise.

    15.
    发明专利
    未知

    公开(公告)号：DE60204189T2

    公开(公告)日：2006-02-02

    申请号：DE60204189

    申请日：2002-06-06

    Applicant: ST MICROELECTRONICS PVT LTD

    Inventor： SINGH MONINDER ,  CHAUDHRY ANURAG

    IPC: H03K19/177

    Abstract: A field programmable logic device comprising at least two independently configurable embedded memory structures wherein said memory structures differ in at least one of the following parameter memory size available configuration depths available configuration widths for efficient memory utilization.

    ELEMENT A RETARD VARIABLE
    17.
    发明专利
    ELEMENT A RETARD VARIABLE 未知

    公开(公告)号：FR3009149A1

    公开(公告)日：2015-01-30

    申请号：FR1357284

    申请日：2013-07-24

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS PVT LTD

    Inventor： LE TUAL STEPHANE ,  SINGH PRATAP NARAYAN

    IPC: H03K5/134 ,  H03F3/45 ,  H03K19/003

    Abstract: L'invention concerne un circuit de retard comprenant : un premier transistor (102) comportant : un noeud de commande couplé à un noeud d'entrée (108) du circuit de retard ; un premier noeud de courant principal couplé à une première tension d'alimentation (VDD) ; et un deuxième noeud de courant principal couplé à un noeud de sortie (106) du circuit de retard ; un deuxième transistor (104) comportant : un noeud de commande couplé au noeud d'entrée ; un premier noeud de courant principal couplé à une deuxième tension d'alimentation (GND) ; et un deuxième noeud de courant principal couplé au noeud de sortie ; et un circuit de polarisation (110) agencé pour générer des première et deuxième tensions de commande différentielles (VBG_, VBG+), pour appliquer la première tension de commande différentielle à un autre noeud de commande (112) du premier transistor et pour appliquer la deuxième tension de commande différentielle à un autre noeud de commande (114) du deuxième transistor.

    Configurable bus with selection of transmission links and clock frequency
    18.
    发明专利
    Configurable bus with selection of transmission links and clock frequency 未知

    公开(公告)号：GB2495931A

    公开(公告)日：2013-05-01

    申请号：GB201118412

    申请日：2011-10-25

    Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS PVT LTD

    Inventor： URZI IGNAZIO ANTONINO ,  SHARMA VIVEK MOHAN

    IPC: G06F13/38

    Abstract: A method for transmitting data on a configurable bus, comprising a number of physical links RD[z], comprises receiving input data on an input bus 10 at one or more of a number of data rates; selecting a number of the physical links on which the data is to be transmitted and a clock frequency at which the data is to be transmitted, based on information relating to the data rate of the input data and the number of links used on the input bus; and driving the physical links to transmit the data. The selection of transmission settings is intended to provide an optimal balance between bandwidth and power consumption. A receiver 20 which receives data in packets on a number of the physical links at a clock frequency, reformats the packets into groups 21 and transmits the reformatted data on an output bus 22 at one of a plurality of data rates, is also disclosed.

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