公开(公告)号：KR1019980076332A

公开(公告)日：1998-11-16

申请号：KR1019970013012

申请日：1997-04-09

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/306

Abstract: 본 발명은 반도체 장치의 게이트 스페이서 형성 공정에서 발생되는 질화막 찌끼 및 반도체 기판의 식각 충격을 방지할 수 있는 반도체 장치의 제조 방법에 관한 것으로, 반도체 기판 상에 게이트 전극층들을 형성하는 공정과, 게이트 전극층들을 포함하여 반도체 기판 상에 스페이서용 질화막을 형성하는 공정과, 스페이서용 질화막 상에 평탄화용 질화막을 형성하는 공정과, 평탄화용 질화막을 BOE 용액을 이용하여 선택적으로 식각하는 공정과, 스페이서용 질화막을 식각하여 게이트 스페이서를 형성하는 공정을 포함한다. 이와 같은 방법에 의해서, 게이트 스페이서 형성 공정에서 발생되는 질화막 찌끼 및 반도체 기판의 식각 충격을 방지할 수 있다.

公开(公告)号：KR1019980005760A

公开(公告)日：1998-03-30

申请号：KR1019960025263

申请日：1996-06-28

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/304

公开(公告)号：KR100416614B1

公开(公告)日：2004-02-05

申请号：KR1020020015149

申请日：2002-03-20

Applicant: 삼성전자주식회사

Inventor： 이진혁 ,  강사윤 ,  권동휘 ,  유지용 ,  신혜수

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device for reinforcing a substructure of a bond pad, comprises: a semiconductor substrate; substructure formed on the semiconductor substrate; interlevel dielectric layer formed on the substructure and including a contact opening comprising separate dots connected to each other; and contact plug formed in the contact opening. An Independent claim is also included for a method of fabricating a semiconductor device comprising: forming a substructure on a semiconductor substrate; forming an interlevel dielectric layer (208) on the substructure; coating and exposing a photoresist layer on the interlevel dielectric layer to transcribe a mesh-like pattern (A) onto the photoresist layer, the mesh-like pattern comprising dots separated by a predetermined interval; developing and etching the exposed interlevel dielectric layer, thus forming a contact opening (210) by connecting the dots through its expansion; and filling the contact opening in the interlevel dielectric layer with a conductive material to form a contact plug.

Abstract translation: 一种用于加强键合焊盘子结构的半导体器件，包括：半导体衬底; 子结构，形成在半导体衬底上; 形成在所述子结构上并且包括接触开口的层间电介质层，所述接触开口包括彼此连接的分离的点; 并在接触开口中形成接触插塞。 还包括独立权利要求以用于制造半导体器件的方法，包括：在半导体衬底上形成子结构; 在所述子结构上形成层间电介质层（208） 在所述层间介电层上涂覆并曝光光致抗蚀剂层以将网状图案（A）转录到所述光致抗蚀剂层上，所述网状图案包括以预定间隔分开的点; 显影并蚀刻暴露的层间电介质层，从而通过将其点扩展而连接点形成接触开口（210） 以及用导电材料填充层间电介质层中的接触开口以形成接触插塞。

公开(公告)号：KR1020020082667A

公开(公告)日：2002-10-31

申请号：KR1020010022388

申请日：2001-04-25

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/3105

Abstract: PURPOSE: A planarizing method of semiconductor devices is provided to improve a planarization of the semiconductor device by forming a dummy pattern on a region having a low pattern density. CONSTITUTION: A semiconductor substrate(30) includes a cell region(32) having relatively high pattern density and step and a peripheral region(31) having relatively low pattern density and step. Effective patterns(33b,34a,34b) are formed on the cell and the peripheral region(32,31). A dummy pattern(DP) having a relatively thick thickness compared to the effective patterns(EPa) is formed between the effective patterns(34a) of the peripheral region(31). An interlayer dielectric(35) is then formed on the entire surface of the resultant structure, and planarized by CMP(Chemical Mechanical Polishing). The thickness of the effective patterns(EPb) in the cell region(32) is relatively thick compared to the thickness of an effective patterns(EPa) in the peripheral region(31).

Abstract translation: 目的：提供半导体器件的平面化方法，通过在具有低图案密度的区域上形成虚拟图案来改善半导体器件的平坦化。 构成：半导体衬底（30）包括具有相对较高图案密度的单元区域（32）和具有相对较低图案密度和步长的台阶和周边区域（31）。 在单元和外围区域（32,31）上形成有效图案（33b，34a，34b）。 在周边区域（31）的有效图案（34a）之间形成具有与有效图案（EPa）相比厚度相对较厚的虚拟图案（DP）。 然后在所得结构的整个表面上形成层间电介质（35），并通过CMP（化学机械抛光）平坦化。 与周边区域（31）中的有效图案（EPa）的厚度相比，单元区域（32）中的有效图案（EPb）的厚度相对较厚。

公开(公告)号：KR1020020007510A

公开(公告)日：2002-01-29

申请号：KR1020000040600

申请日：2000-07-14

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/027

Abstract: PURPOSE: A photomask is provided to prevent the intensity of the light passing through a space region from being excessively increased so that the profile of a photoresist layer pattern confining a fine contact hole and the space region is optimized by a photolithography process, by forming a mask region in the space region of the photomask having a line/space pattern and a contact pattern. CONSTITUTION: A mask material pattern(31) is formed on one surface of a transparent substrate(30), composed of the line/space pattern(35) and the contact pattern(36). The line/space pattern has at least one mask region covering a predetermined region of the space region(32) of the line/space pattern.

Abstract translation: 目的：提供一种光掩模，以防止通过空间区域的光强度过度增加，从而通过光刻工艺优化限定精细接触孔和空间区域的光致抗蚀剂层图案的轮廓，通过形成 具有线/空间图案和接触图案的光掩模的空间区域中的掩模区域。 构成：在由线/空间图案（35）和接触图案（36）组成的透明基板（30）的一个表面上形成掩模材料图案（31）。 线/空间图案具有覆盖线/空间图案的空间区域（32）的预定区域的至少一个掩模区域。

公开(公告)号：KR1020000033700A

公开(公告)日：2000-06-15

申请号：KR1019980050684

申请日：1998-11-25

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/28

Abstract: PURPOSE: A method for forming metal lines of a semiconductor device is provided to prevent a photoresist pattern from distorting using a non-permissive layer. CONSTITUTION: An insulation layer formed on a semiconductor substrate is flattened. A non-permissive layer is formed on the flattened insulation layer. A photoresist layer is formed on the non-permissive layer. The photoresist layer is patterned by a photograph process. The non-permissive layer and flattened insulation layer are continuously etched via the patterned photoresist layer, so that a damascene area is formed.

Abstract translation: 目的：提供一种用于形成半导体器件的金属线的方法，以防止光致抗蚀剂图案使用非允许层变形。 构成：在半导体基板上形成的绝缘层变平。 在平坦化的绝缘层上形成不允许的层。 在非允许层上形成光致抗蚀剂层。 光致抗蚀剂层通过照相工艺图案化。 通过图案化的光致抗蚀剂层连续地蚀刻非允许层和扁平绝缘层，从而形成镶嵌区域。

公开(公告)号：KR1019980079122A

公开(公告)日：1998-11-25

申请号：KR1019970016797

申请日：1997-04-30

Applicant: 삼성전자주식회사

Inventor： 권동휘 ,  송준의

IPC: H01L21/76

Abstract: 본 발명에 의한 돌출 구조물을 구비하는 반도체장치 및 그 제조방법에 관해 개시한다. 본 발명에 의한 반도체장치에서 게이트 적층물의 게이트 보호막 패턴의 측면은 소정의 길이 만큼 돌출되어 있다. 따라서 상기 게이트 보호막 패턴은 상기 게이트 적층물을 구성하는 다른 패턴들에 대해서 우산과 같은 역할을 한다. 상기 게이트 적층물의 측면에는 게이트 스페이서가 형성되어 있는데, 돌출부분에서의 두께는 돌출되지 않은 부분에서의 두께에 비해 얇다. 하지만, 돌출된 부분에서의 게이트 스페이서의 얇음을 상기 게이트 보호막 패턴의 측면 돌출로 보상할 수 있으므로, 결국, 본 발명에 의한 반도체장치에서 게이트 적층물의 측면에는 상, 하 등가 두께를 갖는 게이트 스페이서가 구비되어 있는 것이 된다. 따라서 게이트 스페이서의 상기 게이트 실리사이드층의 모서리 부분의 두께가 두꺼워져서 외부에서의 식각에 대한 상기 게이트 적층물의 내성 특히, 도전성을 갖는 부분의 내성이 강화된다. 이와 같은 게이트 적층물을 포함하는 층간절연막에는 상기 게이트 적층물의 도전성 부분의 노출을 방지하면서 충분히 낮은 콘택저항을 갖는 콘택홀을 형성할 수 있다.

公开(公告)号：KR1020030044195A

公开(公告)日：2003-06-09

申请号：KR1020010074862

申请日：2001-11-29

Applicant: 삼성전자주식회사

Inventor： 김선영 ,  이운경 ,  권동휘

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: PURPOSE: A method for fabricating a gate contact structure is provided to prevent a junction region or an isolation layer pattern from being etched when etching an interlayer dielectric by previously etching a capping pattern in a gate contact hole formation region before the interlayer dielectric is patterned to form a gate contact hole. CONSTITUTION: The isolation layer pattern confining an active area is formed in a semiconductor substrate(100). A gate electrode(175) and the capping pattern(180) are sequentially stacked on the semiconductor substrate including the isolation layer pattern, crossing the isolation layer pattern and the active area. The first gate contact hole(185) exposes an upper surface of a predetermined region of the gate electrode, penetrating the capping pattern. The interlayer dielectric is formed on the semiconductor substrate including the first gate contact hole. The interlayer dielectric is patterned to form an interlayer dielectric pattern(230) with the second gate contact hole(236) exposing the upper surface of the gate electrode wherein the second contact hole penetrates the first gate contact hole.

Abstract translation: 目的：提供一种用于制造栅极接触结构的方法，以在层间电介质图案化之前，通过预先蚀刻栅极接触孔形成区域中的覆盖图案来蚀刻层间电介质时防止接合区域或隔离层图案被蚀刻 形成门接触孔。 构成：限制有源区的隔离层图案形成在半导体衬底（100）中。 栅极电极（175）和封盖图案（180）依次层叠在包括隔离层图案的半导体衬底上，与隔离层图案和有源区域交叉。 第一栅极接触孔（185）露出栅电极的预定区域的上表面，穿过封盖图案。 在包括第一栅极接触孔的半导体衬底上形成层间电介质。 图案化层间电介质以形成层间介电图案（230），其中第二栅极接触孔（236）暴露栅电极的上表面，其中第二接触孔穿过第一栅极接触孔。

公开(公告)号：KR1020010076845A

公开(公告)日：2001-08-16

申请号：KR1020000004251

申请日：2000-01-28

Applicant: 삼성전자주식회사

Inventor： 권동휘

IPC: H01L21/027

Abstract: PURPOSE: A photo mask for transferring a conductive line is provided, which comprises a layout pattern of an improved structure to correspond to a design rule of a semiconductor device. CONSTITUTION: The photo mask comprises a bar/space pattern(II) of an improved structure on a transparent substrate(200). The bar/space pattern(II) comprises a bar pattern(210) comprising a rugged part on its sidewall and a space pattern(220) formed as an upper surface of the transparent substrate between the bar pattern. The bar pattern is formed with a Cr which is a non-transparent material as to a light used in a photo lithography process. If a conductive line is transferred onto a semiconductor substrate with a photo lithography process using the photo mask comprising a layout pattern, an additive interference of a refracted light transmitted with the space pattern is mitigated.

Abstract translation: 目的：提供用于传送导线的光掩模，其包括对应于半导体器件的设计规则的改进结构的布局图案。 构成：光掩模包括在透明基板（200）上具有改进结构的条/空间图案（II）。 杆/空间图案（II）包括在其侧壁上包括粗糙部分的条形图案（210）和在条形图案之间形成为透明基底的上表面的空间图案（220）。 条形图案由与光刻工艺中使用的光不相关的Cr形成。 如果通过使用包括布局图案的光掩模的光刻工艺将导电线转印到半导体衬底上，则减轻了与空间图案一起传输的折射光的附加干涉。

公开(公告)号：KR1020010027677A

公开(公告)日：2001-04-06

申请号：KR1019990039546

申请日：1999-09-15

Applicant: 삼성전자주식회사

Inventor： 조명관 ,  권동휘 ,  이준성

IPC: H01L27/115

Abstract: PURPOSE: A flash memory device and a fabrication method thereof are provided not only to allow a reduction in the area ratio of a bit line contact to a cell but also to reduce with easy the area of the cell. CONSTITUTION: The flash memory device includes a gate stack composed of a floating gate(54), an interlayer dielectric(56), a polysilicon layer(58) forming a control gate together with an overlying tungsten silicon layer(60), and a silicon nitride layer(62). A drain(66) and a source(68) are formed in a silicon substrate(50), and a spacer is formed on a sidewall of the gate stack. The first insulating layer(70) is then formed and etched to form self-aligned contact holes therein while reducing the cell area. The contact holes are filled with the first bit line contact(72) and a common source line contact(74), and the second insulating layer(76) is then formed thereon. Thereafter, a common source line(78) is formed on the common source line contact(74) and covered with the third insulating layer(80). The second bit line contact(82) is then formed on the first bit line contact(72), and a bit line(84) is finally formed.

Abstract translation: 目的：提供一种闪速存储器件及其制造方法，不仅可以减少与单元电池的位线接触的面积比，而且可以容易地减小电池的面积。 闪存器件包括由浮置栅极（54），层间电介质（56），与上覆钨硅层（60）一起形成控制栅极的多晶硅层（58）和硅层 氮化物层（62）。 在硅衬底（50）中形成漏极（66）和源极（68），并且在栅极叠层的侧壁上形成间隔物。 然后形成并蚀刻第一绝缘层（70）以在其中形成自对准接触孔，同时减小电池区域。 接触孔填充有第一位线接触件（72）和公共源极线接触件（74），然后在其上形成第二绝缘层（76）。 此后，共用源极线（78）形成在公共源极线接触部（74）上，被第三绝缘层（80）覆盖。 然后，第二位线触点（82）形成在第一位线触点（72）上，并且最终形成位线（84）。