公开(公告)号：KR100366622B1

公开(公告)日：2003-01-09

申请号：KR1020000037397

申请日：2000-06-30

Applicant: 삼성전자주식회사

Inventor： 김형준 ,  남병윤 ,  박경원

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/76801

Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract translation: 提供了一种用于形成半导体器件的导电触点的方法。 根据本发明的一个方面，在半导体衬底上形成伪介电层图案，该伪介电层图案具有伪开口和具有比伪介电层更低的蚀刻速率的用于填充伪开口的中间介电层图案。 选择性地去除使用中间层图案作为蚀刻掩模的伪介电层图案，以及用于暴露伪介电层图案所在的部分的半导体衬底的接触开口。

公开(公告)号：KR100327339B1

公开(公告)日：2002-03-06

申请号：KR1019990040652

申请日：1999-09-21

Applicant: 삼성전자주식회사

Inventor： 박정우 ,  송원상 ,  박태서 ,  이한신 ,  박경원

IPC: H01L21/324

Abstract: 반도체웨이퍼또는반도체소자의기판표면에존재하는결함들을큐어링하고, 그에기인한표면거칠기를개선시키는어닐링을수반한반도체웨이퍼및 반도체소자의제조방법이개시된다. 반도체웨이퍼의제작단계또는반도체소자의특정공정단계에서발생된표면결함들이존재하는반도체웨이퍼또는반도체소자를 10Torr 이하의고진공, 950℃이하의저온및 반도체물질소오스가스를포함하는수소가스분위기하에서어닐링시킨다. 본발명의어닐링이주로적용되는것은웨이퍼를제작하기위한폴리싱단계, 반도체소자를제조하기위한각종이온주입단계, 건식식각단계, 화학적및 기계적폴리싱단계들이있다. 본발명에의하면, 저온에서단시간내에어닐링이이루어지기때문에소자의신뢰성및 경제성이향상된다.

公开(公告)号：KR1020020009670A

公开(公告)日：2002-02-02

申请号：KR1020000043002

申请日：2000-07-26

Applicant: 삼성전자주식회사

Inventor： 박경원

IPC: H04B7/155

CPC classification number: H04L43/103 ,  H04L1/0058

Abstract: PURPOSE: A method for automatically driving a board in a communication system is provided to shorten a service ready time according to shape change and stably operate a system by automatically recognizing the shape change when a shape is changed and being composed as a state capable of service. CONSTITUTION: A fault block composed in a BSC(Base Station Controller) and a BTS(Base Transceiver Station) periodically polls whether a hardware board is mounted and detects whether the hardware board is mounted(211). When the mount of a new board is detected, the fault block provides mounting information to a composition block(213,215). The composition block changes database information on the basis of provided mounting information(219,225). After the database information is changed, the composition block informs changed contents to an association block(221,227). If the correction of association information according to the new board mounting is completed, the composition provides a corresponding function to the new board and drives the new block(223,229,231).

Abstract translation: 目的：提供一种在通信系统中自动驱动板的方法，以根据形状变化缩短服务就绪时间，并且通过在形状改变时自动识别形状变化并且被构成为能够服务的状态来稳定地操作系统 。 构成：在BSC（基站控制器）和BTS（基站收发台）中组成的故障块周期性地轮询硬件板是否被安装，并检测硬件板是否被安装（211）。 当检测到新电路板的安装时，故障块向组合块提供安装信息（213,215）。 组合块根据提供的安装信息更改数据库信息（219,225）。 在更改数据库信息之后，合成块将改变的内容通知给关联块（221,227）。 如果根据新板安装的关联信息的修正完成，则组合为新板提供相应的功能并驱动新块（223,229,231）。

公开(公告)号：KR1020010046448A

公开(公告)日：2001-06-15

申请号：KR1019990050224

申请日：1999-11-12

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  박경원 ,  김성진

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: PURPOSE: A method for manufacturing an isolating layer wherein a divot is prevented and a process is simplified, is provided to simplify a manufacturing process by forming a trench by using a photoresist layer pattern as an etching mask, and to use a thin nitride layer liner for a double purpose wherein the nitride layer liner in a trench prevents the sidewall of the trench from being oxidized and the nitride layer liner on a semiconductor substrate functions as a planarization stop layer. CONSTITUTION: A trench is formed in a semiconductor substrate(100). A thermal oxide layer(118) is formed on the entire surface of the semiconductor substrate having the trench. A nitride layer liner(119) is formed on the thermal oxide layer. The trench is filled with a gap fill isolation layer while the nitride layer liner formed in an upper corner of the trench is eliminated. The entire surface of the semiconductor substrate is planarized by using the nitride layer liner as a planarization stop layer. The nitride layer liner exposed in planarizing the gap fill isolation layer is eliminated.

Abstract translation: 目的：提供一种制造隔离层的方法，其中防止纹理并简化工艺，以通过使用光致抗蚀剂层图案作为蚀刻掩模通过形成沟槽来简化制造工艺，并且使用薄的氮化物层衬垫 为了双重目的，其中沟槽中的氮化物层衬垫防止沟槽的侧壁被氧化，并且半导体衬底上的氮化物层衬垫用作平坦化停止层。 构成：在半导体衬底（100）中形成沟槽。 在具有沟槽的半导体衬底的整个表面上形成热氧化物层（118）。 氮化物层衬垫（119）形成在热氧化物层上。 沟槽填充有间隙填充隔离层，同时消除了形成在沟槽的上角中的氮化物层衬垫。 通过使用氮化物层衬垫作为平坦化停止层，使半导体衬底的整个表面平坦化。 消除了在平坦化间隙填充隔离层中暴露的氮化物层衬垫。

公开(公告)号：KR1020010038795A

公开(公告)日：2001-05-15

申请号：KR1019990046911

申请日：1999-10-27

Applicant: 삼성전자주식회사

Inventor： 김성의 ,  강호규 ,  박경원

IPC: H01L21/316

Abstract: PURPOSE: A method for manufacturing a dual gate oxide layer of different thickness of a semiconductor device is provided to prevent the first gate oxide layer from being weakened in a subsequent process, by inducing a passivation layer on the firstly-induced first gate oxide layer to form the dual gate oxide layer. CONSTITUTION: The first gate oxide layer(200) is formed on a semiconductor substrate(100). A passivation layer(300) is formed on the first gate oxide layer. A photoresist pattern is formed on the passivation layer. A part of the passivation layer and the first gate oxide layer is selectively etched to expose the surface of the semiconductor substrate by using the photoresist pattern as an etching mask. The remaining first gate oxide layer is protected by the remaining passivation layer, and the photoresist pattern is eliminated. The second gate oxide layer having a thickness different than that of the first gate oxide layer is formed on the exposed semiconductor substrate.

Abstract translation: 目的：提供一种用于制造半导体器件的不同厚度的双栅极氧化物层的方法，以防止在随后的工艺中第一栅氧化层被削弱，通过在第一感应的第一栅极氧化物层上诱导钝化层 形成双栅氧化层。 构成：第一栅极氧化物层（200）形成在半导体衬底（100）上。 在第一栅极氧化物层上形成钝化层（300）。 在钝化层上形成光刻胶图形。 通过使用光致抗蚀剂图案作为蚀刻掩模，选择性地蚀刻钝化层和第一栅极氧化物层的一部分以暴露半导体衬底的表面。 剩余的第一栅极氧化物层被剩余的钝化层保护，并且消除光刻胶图案。 在暴露的半导体衬底上形成具有与第一栅极氧化物层的厚度不同的厚度的第二栅极氧化物层。

公开(公告)号：KR100287182B1

公开(公告)日：2001-04-16

申请号：KR1019980043840

申请日：1998-10-20

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  신유균 ,  이한신 ,  박경원

IPC: H01L21/76

Abstract: 반도체 장치의 소자분리막 형성방법에 관해 개시되어 있다. 트랜치의 측면 상부에 활성영역의 가장자리와 소자분리막의 안쪽을 이어주는 스페이서를 갖는 소자분리막 형성방법이 개시되어 있다. 여기서, 상기 스페이서는 상기 트랜치의 측면 상부와 예각을 이룬다. 따라서, 후속 게이트 산화막 형성공정에서 상기 활성영역의 전영역 상에 균일한 두께로 게이트 산화막을 형성할 수 있다. 상기 활성영역의 상기 트랜치와 접하는 가장자리 부분도 예외는 아니다. 이와 같이, 본 발명에 의한 소자분리막 형성방법에 의해 균일한 두께로 게이트 산화막을 형성할 수 있으므로 게이트 산화막의 특성이 저하되는 것을 방지할 수 있고 그 결과, 게이트 산화막의 신뢰성이 상실되는 것을 방지할 수 있다. 더욱이, 상기 소자분리막의 고밀도화가 1150℃정도의 고온에서 실시되므로 상기 소자분리막내의 모든 스트레스를 해소할 수 있다.

公开(公告)号：KR1020000031181A

公开(公告)日：2000-06-05

申请号：KR1019980047090

申请日：1998-11-04

Applicant: 삼성전자주식회사

Inventor： 박경원

IPC: G06F15/16

Abstract: PURPOSE: An internal data communication method of the base station management system between process is provided to prevent the loss of an input data and to process separately the input data in the base station management system. CONSTITUTION: An input processor(310) comprised in a data communication interface unit(210) receives a system management information data inputted from a network connection part. A system configuration data processor(313) checks periodically whether the system management information data is stored in a buffering part(311). A 1st processing processor(351) to a Nth processing processor(35N) check whether the data is stored in its massage queue. A 1st interface processor(331) to a Nth interface processor(33N) check a received file queue(370) periodically. In case that the data stored in the buffering part(311) is a statistical data, a statistical data processor(314) stores the data in an area equivalent to a storage part(140). If a system operator inputs a system operation and maintenance associated command language through a display unit, an associated interface processor among the 1st interface processor(331) to the Nth interface processor(33N) stores the command language in an associated area of a transmitted file queue(380).

Abstract translation: 目的：提供基站管理系统之间的内部数据通信方法，以防止丢失输入数据，并单独处理基站管理系统中的输入数据。 构成：包括在数据通信接口单元（210）中的输入处理器（310）接收从网络连接部分输入的系统管理信息数据。 系统配置数据处理器（313）周期性地检查系统管理信息数据是否存储在缓冲部分（311）中。 第一处理处理器（351）到第N处理器（35N）检查数据是否存储在其按摩队列中。 第一接口处理器（331）到第N接口处理器（33N）周期性地检查接收到的文件队列（370）。 在存储在缓冲部分（311）中的数据是统计数据的情况下，统计数据处理器（314）将数据存储在与存储部分相当的区域中。 如果系统操作者通过显示单元输入系统操作和维护相关联的命令语言，则第一接口处理器（331）到第N接口处理器（33N）中的关联接口处理器将命令语言存储在发送文件的相关区域中 队列（380）。

公开(公告)号：KR100258140B1

公开(公告)日：2000-06-01

申请号：KR1019970069983

申请日：1997-12-17

Applicant: 삼성전자주식회사

Inventor： 박경원 ,  설홍수

IPC: H04M11/00

Abstract: PURPOSE: A voice recognizing device and method of a voice mailing device are provided to decrease a searching time by using numerous processors in order to search a word for voice recognition. CONSTITUTION: When a user inputs a word for voice recognition with voice(311), voice characteristic extracting parts extracts a characteristic(313), and store the characteristic at a buffer, and report a finish of the extraction to a control part(315). The control part copies the characteristic, and stores the characteristic at each input buffer of two voice recognition word searching parts(317). After this, the two voice recognition word searching parts find the most similar word at each database by using the characteristic, and report the most similar words to the control part(321). The control part selects the most similar word among received words from the two voice recognition word searching parts(323).

Abstract translation: 目的：提供语音邮件装置的语音识别装置和方法，以通过使用多个处理器来减少搜索时间，以搜索单词以进行语音识别。 构成：当用户输入用于具有语音（311）的语音识别的单词时，语音特征提取部分提取特征（313）并将特征存储在缓冲器上，并将提取结束报告给控制部分（315） 。 控制部分复制特征，并将特性存储在两个语音识别词搜索部分（317）的每个输入缓冲器处。 之后，两个语音识别词搜索部分通过使用该特征在每个数据库中找到最相似的词，并向控制部分报告最相似的词（321）。 控制部分从两个语音识别词搜索部分（323）中选择接收到的单词中最相似的单词。

公开(公告)号：KR1020000026333A

公开(公告)日：2000-05-15

申请号：KR1019980043840

申请日：1998-10-20

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  신유균 ,  이한신 ,  박경원

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to increase a reliability of a gate oxidation by forming a gate oxide having a constant thickness. CONSTITUTION: A method for forming an isolation layer of a semiconductor device is to dissolve a stress inside an isolation layer and improve a center portion of the isolation layer contacted to an upper portion of a trench. The method comprises the steps of: setting an active area and a field area on a semiconductor substrate(40); forming a mask layer pattern composed with a first and a second mask pattern on the active area; forming a trench(46) on the field area; forming a first insulating layer to fill the trench on the mask pattern; forming the first insulating layer of a high density; forming a first isolation layer; forming a spacer on a side face of the second mask layer pattern; etching the first isolation layer; removing the second mask pattern and the spacer; and forming a second isolation layer(50b).

Abstract translation: 目的：提供一种用于形成半导体器件的隔离层的方法，以通过形成具有恒定厚度的栅极氧化物来增加栅极氧化的可靠性。 构成：用于形成半导体器件的隔离层的方法是将应力溶解在隔离层内部并改善与沟槽的上部接触的隔离层的中心部分。 该方法包括以下步骤：在半导体衬底（40）上设置有源区和场区; 在所述有效区域上形成由第一和第二掩模图案组成的掩模层图案; 在所述场区域上形成沟槽（46）; 形成第一绝缘层以填充所述掩模图案上的沟槽; 形成高密度的第一绝缘层; 形成第一隔离层; 在所述第二掩模层图案的侧面上形成间隔物; 蚀刻第一隔离层; 去除第二掩模图案和间隔物; 和形成第二隔离层（50b）。

公开(公告)号：KR200176432Y1

公开(公告)日：2000-04-15

申请号：KR2019980001039

申请日：1998-01-31

Applicant: 삼성전자주식회사

Inventor： 박경원

IPC: D06F39/02

Abstract: 시중에서 구입한 세제 용기를 세탁기의 세제 투입구에 설치하여 세탁시 세제를 세탁기의 내부로 공급하도록 한 세탁기의 세제용기가 개시된다. 세탁기의 커버 톱에 마련된 세제 투입구와, 세제 투입구와 결합되어 세제를 세탁기의 내부로 공급하는 세제 용기에 있어서, 세제를 담겨지는 통 몸체와, 상기 세제 투입구와 결합되며 그 상단에 세제가 쏟아지는 것을 방지하는 보호막이 부착되고, 상기 통 몸체에 마련된 세제 배출구를 구비하는 것을 특징으로 한다. 따라서, 시중에서 구입하는 세제용기를 세탁기에 설치할 수 있기 때문에, 종래와 같이 세제를 별도의 세제통에 도구를 이용하여 덜어야 하는 번거로움을 해소할 수 있다.