公开(公告)号：KR100611122B1

公开(公告)日：2006-08-09

申请号：KR1020000003282

申请日：2000-01-24

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  정민제

IPC: H01L21/304

Abstract: 연마 패드를 사용한 연마로 생성되는 스크레치를 제거하는 방법 및 이를 이용한 반도체 장치의 패턴 형성 방법이 개시되어 있다. 연마 패드를 사용한 연마를 통하여 반도체 기판상에 형성한 피가공막의 표면을 평탄하게 형성한 다음 상기 피가공막 표면을 에치백하여 상기 피가공막을 연마할 때 상기 피가공막 표면에 생성된 스크레치를 제거한다. 패턴을 형성할 때는, 절연막을 하부 구조물이 형성된 반도체 기판상에 형성하고, 상기 절연막을 연마 패드로 연마하여 상기 절연막 표면을 평탄하게 형성한다. 상기 절연막 표면을 에치백하여 상기 절연막을 연마할 때 상기 절연막 표면에 생성된 스크레치를 제거한다. 상기 절연막의 소정 부위를 에칭하여 개구부를 갖는 절연막을 형성한다. 상기 에치백을 통하여 스크레치를 용이하게 제거할 수 있다.

公开(公告)号：KR1020040042915A

公开(公告)日：2004-05-22

申请号：KR1020020070866

申请日：2002-11-14

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  고동환

IPC: H01L21/66

Abstract: PURPOSE: A hardware system for selectively rejecting a non-operational chip in a wafer is provided to be capable of reducing chip loss. CONSTITUTION: A hardware system is provided with a display monitor module(100) for displaying a non-operational chip of a wafer and a work control module(200) for pursuing the non-operational chip displayed at the display monitor module and precisely controlling focus. The hardware system further includes a failure chip display module(300) capable of selectively displaying the non-operational chip. Preferably, the work control module includes a scroll bar for pursuing the non-operational chip and a focus control part. Preferably, the non-operational chip display module is capable of carrying out an ink treatment on the non-operational chip.

Abstract translation: 目的：提供用于选择性地拒绝晶片中的非操作芯片的硬件系统以能够减少芯片损耗。 构成：硬件系统具有用于显示晶片的非操作芯片的显示监视器模块（100）和用于追踪在显示监视器模块上显示的非操作芯片并且精确地控制焦点的工作控制模块（200） 。 硬件系统还包括能够选择性地显示非操作芯片的故障芯片显示模块（300）。 优选地，工作控制模块包括用于追踪非操作芯片的滚动条和聚焦控制部分。 优选地，非操作芯片显示模块能够对非操作芯片进行墨处理。

公开(公告)号：KR1020020041180A

公开(公告)日：2002-06-01

申请号：KR1020000070975

申请日：2000-11-27

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  윤석훈

IPC: H01L21/304

Abstract: PURPOSE: A cleansing method of semiconductor devices is provided to reduce residues of a substrate by performing an additional wet cleansing after removing contaminated material with material layer. CONSTITUTION: A material layer(110) made of a photoresist is formed on the entire surface of a substrate(100) deposited with a contaminated material such as particles(106). Then, the resultant structure is performed with a thermal treatment. The contaminated material is then removed by removing the material layer(110) in the same time. At this time, the removing process of the material layer is O2 plasma ashing. A wet cleansing is performed on the entire surface of the material layer and contaminated material removed substrate(100). At this time, the wet cleansing is additional cleansing.

Abstract translation: 目的：提供半导体器件的清洁方法，通过在用材料层除去受污染的材料之后执行附加的湿法清洁来减少基底的残留。 构成：在沉积有污染物质如颗粒（106）的基底（100）的整个表面上形成由光致抗蚀剂制成的材料层（110）。 然后，通过热处理进行所得到的结构。 然后通过同时去除材料层（110）来除去受污染的材料。 此时，材料层的去除过程为O2等离子体灰化。 在材料层的整个表面和被污染的材料移除的基板（100）上进行湿式清洁。 此时，湿法清洁是额外的清洁。

公开(公告)号：KR1020000055478A

公开(公告)日：2000-09-05

申请号：KR1019990004122

申请日：1999-02-06

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  김성환 ,  석종욱

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a butting contact of a semiconductor device is to prevent over etch and etch stopping phenomena of a middle conductive layer during the formation of the butting contact hole. CONSTITUTION: A method for forming a butting contact of a semiconductor device comprises the steps of: providing a semiconductor substrate having a lower conductive layer(100) formed thereon; forming a first insulating layer(102) on the lower conductive layer; forming a middle conductive layer(104) on the first insulating layer; forming a second insulating layer(105) and a third insulating layer(106) on the middle conductive layer in which the second insulating layer has a different etch selectivity from the first and third insulating layer; and etching the third insulating layer and the first insulating layer orderly to form a butting contact hole(108) such that a part of the lower conductive layer and the middle conductive layer is exposed.

Abstract translation: 目的：形成半导体器件的对接接触的方法是在形成对接接触孔期间防止中间导电层的过蚀刻和蚀刻停止现象。 构成：用于形成半导体器件的对接接触的方法包括以下步骤：提供其上形成有下导电层（100）的半导体衬底; 在所述下导电层上形成第一绝缘层（102）; 在所述第一绝缘层上形成中间导电层（104）; 在所述中间导电层上形成第二绝缘层（105）和第三绝缘层（106），其中所述第二绝缘层具有与所述第一和第三绝缘层不同的蚀刻选择性; 并且有选择地蚀刻第三绝缘层和第一绝缘层以形成对接接触孔（108），以使得下导电层和中间导电层的一部分露出。

公开(公告)号：KR1020000041362A

公开(公告)日：2000-07-15

申请号：KR1019980057221

申请日：1998-12-22

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  윤석훈 ,  정민제 ,  김홍일 ,  이형규 ,  김남중

IPC: H01L21/265

Abstract: PURPOSE: A method of manufacturing a semiconductor device is to preclude the difference of an etch rate due to the difference of a pattern density, namely a loading effect, form being generated. CONSTITUTION: A method of manufacturing a semiconductor device, in which a prescribed film formed within an area(105) with high pattern density and an area(106) with low pattern density is etched, comprises the steps of: ion-implanting an impurity ion in an area having relative low etch rate against the prescribed film among the area with high pattern density and the area with low pattern density; forming an etching mask on the prescribed film and the ion-implanted film; etching simultaneously the prescribed film and the ion-implanted film using the etching mask to form a pattern(102a,103a); and removing the etching mask.

Abstract translation: 目的：一种制造半导体器件的方法是排除由于图案密度的不同而引起的蚀刻速率的差异，即形成的负载效应。 构成：一种制造半导体器件的方法，其中蚀刻形成在具有高图案密度的区域（105）内的规定膜和具有低图案密度的区域（106）的半导体器件包括以下步骤：离子注入杂质离子 在具有高图案密度的区域和具有低图案密度的区域中相对于规定膜具有相对低的蚀刻速率的区域; 在规定的膜和离子注入膜上形成蚀刻掩模; 使用蚀刻掩模同时蚀刻规定的膜和离子注入膜以形成图案（102a，103a）; 并去除蚀刻掩模。

公开(公告)号：KR1020000030956A

公开(公告)日：2000-06-05

申请号：KR1019980044411

申请日：1998-10-22

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  김남중 ,  김홍일 ,  정민제 ,  박재현

IPC: H01L21/306

Abstract: PURPOSE: A method for etching a polysilicon for forming a gate electrode is provided to reduce a tail generated in a bottom part of the gate electrode and to obtain a vertical profile by increasing an out gassing effect according to the reduction of the pattern size. CONSTITUTION: A preventing film of reflection and a polysilicon film are successively etched in an etching chamber by using a photoresist film as a mask. Herein, a certain thickness of the polysilicon film is etched by using 10-100sccm of Cl2 gas, 20-60sccm of SF6 gas, 20-200sccm CF4 gas, or 0-20sccm of HeO2 gas in a pressure for 20-100mTorr and a power for 150-400W. And then, the remained polysilicon film is etched by using 10-100sccm of Cl2 gas and 30-150sccm of HBr gas in the pressure for 75-200mTorr and the power for 50-300W to form a gate electrode(104a). Herein, the side of a top part(B) is 230mm, and the size of a bottom part(A) is 250mm. Therefore, a tail generated in the bottom part of the gate electrode and a polymer are reduced while obtaining a vertical profile.

Abstract translation: 目的：提供一种用于蚀刻用于形成栅电极的多晶硅的方法，以减少在栅电极的底部产生的尾部，并且通过根据图案尺寸的减小增加放气效果来获得垂直轮廓。 构成：通过使用光致抗蚀剂膜作为掩模，在蚀刻室中连续蚀刻防反射膜和多晶硅膜。 这里，通过使用10-100sccm的Cl 2气体，20-60sccm的SF 6气体，20-200sccm的CF 4气体或者0〜20sccm的HeO 2气体在20-100mTorr的压力下蚀刻多晶硅膜的一定厚度， 150-400W。 然后，通过使用10-100sccm的Cl 2气体和在压力为75-200mTorr的30-150sccm的HBr气体蚀刻剩余的多晶硅膜，并且为50-300W的功率蚀刻形成栅电极（104a）。 这里，顶部（B）的一侧为230mm，底部（A）的尺寸为250mm。 因此，在栅电极的底部和聚合物中产生的尾部减少，同时获得垂直轮廓。

公开(公告)号：KR100611109B1

公开(公告)日：2006-08-09

申请号：KR1020000001781

申请日：2000-01-14

Applicant: 삼성전자주식회사

Inventor： 이현철 ,  정민제 ,  이경주 ,  김동윤

IPC: H01L21/66

Abstract: 웨이퍼를 절단하지 않고서도 용이하게 콘택홀의 개구 유무를 확인할 수 있는 반도체 장치의 콘택홀 검사 방법이 개시되어 있다. 먼저, 실리콘 기판의 상부에 트랜지스터를 형성하고 이의 상부에 층간절연막을 형성도록 한다. 이후 상기 층간절연막을 식각하여 상기 트랜지스터의 소오스/드레인 영역과 스토리지 노드의 연결을 위한 콘택홀을 형성한다. 상기 콘택홀내에 노출된 실리콘의 손상 깊이에 따라 반사되는 파장이 달라지는 특정 파장의 열선을 상기 실리콘 기판에 입사시킨 후 반사되는 파장을 검사하도록 한다. 열선의 입사 파장과 반사 파장의 비를 구하여 이 값에 준하여 실리콘 기판이 손상을 입은 정도, 즉, 콘택홀의 개구 유무를 판단할 수 있다. 열선을 이용하여 실리콘 기판 표면의 손실 정도를 측정하는 것에 의해 수행되므로 웨이퍼를 파괴하지 않고도 콘택홀의 개구 유무를 용이하게 검사할 수 있기 때문에 시간과 비용이 절감된다.

公开(公告)号：KR1020030063056A

公开(公告)日：2003-07-28

申请号：KR1020020003616

申请日：2002-01-22

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  손권

IPC: H01L21/3065

Abstract: PURPOSE: A method of forming a contact hole in a semiconductor device is provided to achieve a contact hole having a tilt and a bend at sidewalls of the contact hole. CONSTITUTION: The first insulation layer having its thickness and a sacrificial thickness(h2) is formed on a semiconductor substrate(26). A photoresist pattern is formed on a portion of the first insulation layer. The second insulation layer(24a) is formed by anisotropic etching to form a groove on the first insulation layer. The photoresist pattern remaining on the second insulation layer is removed. By etch back of the second insulation layer as thick(h1) as the sacrificial thickness, A contact hole is exposed on the semiconductor substrate.

Abstract translation: 目的：提供一种在半导体器件中形成接触孔的方法，以实现在接触孔的侧壁处具有倾斜和弯曲的接触孔。 构成：在半导体衬底（26）上形成其厚度和牺牲厚度（h2）的第一绝缘层。 在第一绝缘层的一部分上形成光致抗蚀剂图案。 第二绝缘层（24a）通过各向异性蚀刻形成在第一绝缘层上形成凹槽。 去除残留在第二绝缘层上的光致抗蚀剂图案。 通过第二绝缘层的回蚀刻作为牺牲厚度的厚（h1），在半导体衬底上露出接触孔。

公开(公告)号：KR1020020005787A

公开(公告)日：2002-01-18

申请号：KR1020000039180

申请日：2000-07-10

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  윤석훈

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a metal line of a semiconductor device is provided to deposit easily a diffusion barrier layer and form a metal layer of a low resistance by improving a profile of a via contact. CONSTITUTION: The first metal layer(32a) is formed on a semiconductor substrate(30). An anti-reflective layer(34b) is formed on the first metal layer. A metal layer pattern(36a) is formed by patterning the first metal layer(32a). An interlayer dielectric(38a) is formed by depositing an insulating layer on the first metal layer pattern(36a) and the semiconductor substrate(30). The interlayer dielectric(38a) is flattened. The first opening portion is formed by etching the interlayer dielectric(38a). The second opening portion is formed by etching the anti-reflective layer(34b). A barrier metal layer(44) is formed by depositing an alloy on each side and each surface of the first and the second opening portions. The second metal layer(46) is deposited thereon.

Abstract translation: 目的：提供一种形成半导体器件的金属线的方法，通过改善通孔接触的轮廓，容易地沉积扩散阻挡层并形成低电阻的金属层。 构成：第一金属层（32a）形成在半导体衬底（30）上。 在第一金属层上形成抗反射层（34b）。 通过图案化第一金属层（32a）形成金属层图案（36a）。 通过在第一金属层图案（36a）和半导体衬底（30）上沉积绝缘层来形成层间电介质（38a）。 层间电介质（38a）变平。 通过蚀刻层间电介质（38a）形成第一开口部分。 通过蚀刻抗反射层（34b）形成第二开口部分。 通过在第一和第二开口部分的每个侧面和每个表面上沉积合金来形成阻挡金属层（44）。 第二金属层（46）被沉积在其上。

公开(公告)号：KR1020010076029A

公开(公告)日：2001-08-11

申请号：KR1020000003282

申请日：2000-01-24

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  정민제

IPC: H01L21/304

Abstract: PURPOSE: A method for removing a scratch is provided to easily remove a scratch generated when a film to be polished is polished and a method for forming a pattern is provided to minimize badness by the scratch. CONSTITUTION: The method for removing the scratch includes two steps. The first step is to flatly form the surface of a film(22) to be processed by polishing the film formed on a semiconductor substrate(20) with a polishing pad. The second step is to remove a scratch generated on the surface of the film to be processed when the film is polished by etching back the surface of the film. The method for forming a pattern of the semiconductor device includes fourth steps. The first step is to form an insulating film a semiconductor substrate on which a lower structure is formed. The second step is to polish the insulating film with a polishing pad to flatly form the surface of the insulating film. The third step is to remove a scratch generated on the surface of a film to be polished when the insulating film is polished by etching back the surface of the insulating film. The fourth step is to form an insulating film having an opened portion by etching a predetermined part of the insulating film.

Abstract translation: 目的：提供一种去除划痕的方法，以便容易地除去当待抛光的膜被抛光时产生的划痕，并且提供了用于形成图案的方法以通过划痕来最小化不良。 构成：删除划痕的方法包括两个步骤。 第一步骤是通过用抛光垫对形成在半导体衬底（20）上的膜进行抛光来平坦地形成待加工的膜（22）的表面。 第二步是通过蚀刻膜的表面来去除当被抛光的薄膜的表面上产生的划痕。 形成半导体器件的图案的方法包括第四步骤。 第一步是形成其上形成有下部结构的半导体衬底的绝缘膜。 第二步是用抛光垫抛光绝缘膜，以平整地形成绝缘膜的表面。 第三步是通过蚀刻绝缘膜的表面来去除在抛光绝缘膜时在待抛光膜表面产生的划痕。 第四步是通过蚀刻绝缘膜的预定部分来形成具有开口部分的绝缘膜。