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公开(公告)号：KR1020130079057A
公开(公告)日：2013-07-10
申请号：KR1020120000311
申请日：2012-01-02
Applicant: 삼성전자주식회사
CPC classification number: G11C16/16 , G11C11/5635 , G11C16/3445 , G11C2211/5621
Abstract: PURPOSE: A memory controller, a memory device, and an operation method of a system including the same are provided to improve performance by performing each erase operation of an SLC block and an MLC block in different modes. CONSTITUTION: A memory controller controls the operation of a NAND memory device including an MLC block and an SLC block. It is determined that which one of the SLC block and the MLC block is erased. A first command set without a mode selection command and a second command set (CMDSET2) with the mode selection command are generated based on a determination result.
Abstract translation: 目的：通过以不同的模式执行SLC块和MLC块的每个擦除操作，提供包括该存储器的系统的存储器控制器，存储器件和操作方法以提高性能。 构成：存储器控制器控制包括MLC块和SLC块的NAND存储器件的操作。 确定SLC块和MLC块中的哪一个被擦除。 基于确定结果生成不具有模式选择命令的第一命令集和具有模式选择命令的第二命令集（CMDSET2）。
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公开(公告)号：KR1020130043534A
公开(公告)日：2013-04-30
申请号：KR1020110107750
申请日：2011-10-20
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G06F12/0246 , G11C2216/14
Abstract: PURPOSE: A flash memory device and a method for programming the same are provided to increase an operation speed by reducing programming time. CONSTITUTION: Randomized data is inputted by using a seed for a target block. A buffer block(110) is programmed. A page buffer(130) reads the buffer block. The page buffer programs a target block(120) without outputting data from the read buffer block.
Abstract translation: 目的：提供闪存设备及其编程方法，以通过减少编程时间来提高操作速度。 构成：通过使用目标块的种子输入随机数据。 缓冲块（110）被编程。 页面缓冲器（130）读取缓冲器块。 页缓冲器对目标块（120）进行编程，而不从读缓冲块输出数据。
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公开(公告)号：KR1020130042371A
公开(公告)日：2013-04-26
申请号：KR1020110106636
申请日：2011-10-18
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454
Abstract: PURPOSE: A nonvolatile memory device and a programming method thereof are provided to improve a program speed by reducing the number of program loops for a program. CONSTITUTION: A memory cell to which a first program pulse is applied is programmed with one of first to i-th program states after the first program pulse is applied to the memory cell with a first program method(S120). The memory cell to which a second program pulse is applied is programmed with one of (i+1)-th to j-th program states after the second program pulse is applied to the memory cell with a second program method(S140). The second program method is different from the first program method in a step voltage, a bit line forcing voltage, or a verification operation. [Reference numerals] (S120) Programming a memory cell to which a first program pulse is applied with one of first to i-th program states after the first program pulse is applied to the memory cell with a first program method; (S140) Programming the memory cell to which a second program pulse is applied with one of (i+1)-th to j-th program states after second program pulse is applied to the memory cell with a second program method different from at least one selected from step voltage, bit line forcing voltage, and verification operation of the first program method;
Abstract translation: 目的：提供非易失性存储器件及其编程方法，通过减少程序的程序循环数来提高程序速度。 构成：使用第一程序方法将第一编程脉冲施加到存储单元之后，将第一编程脉冲施加到的存储单元以第一至第i程序状态之一进行编程（S120）。 在第二编程脉冲以第二编程方法施加到存储单元之后，第（i + 1）至第j编程状态中的一个被编程到其上应用了第二编程脉冲的存储单元（S140）。 第二程序方法与阶梯电压，位线强制电压或验证操作中的第一编程方法不同。 （附图标记）（S120）在利用第一编程方法将第一编程脉冲施加到存储单元之后，对第一编程脉冲施加第一至第i编程状态之一的存储单元进行编程; （S140）使用第二编程方法将第二编程脉冲之后的第（i + 1）至第j编程状态之一施加到第二编程脉冲之一的存储单元编程到具有不同于至少 选自步进电压，位线强制电压和第一程序方法的验证操作;
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公开(公告)号：KR1020130037087A
公开(公告)日：2013-04-15
申请号：KR1020110101434
申请日：2011-10-05
Applicant: 삼성전자주식회사
IPC: G11C16/12
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12
Abstract: PURPOSE: A nonvolatile memory device and a programming method thereof are provided to reduce power consumption in a program operation by applying an inhibition voltage to each bit line in each program loop. CONSTITUTION: A first program pulse and a second program pulse for programming a memory cell are successively applied with one or more corresponding program states among first to n-th program states. The first program pulse is applied to a bit line connected to the memory cell with the first to n-th program states instead of an inhibition voltage(S120). The inhibition voltage is applied to the bit line connected to the memory cell to be programmed with the program state corresponding to the first program pulse(S140). A second program pulse is applied(S160). [Reference numerals] (S120) Applying a first program pulse instead of an inhibition voltage to a bit line connected to a memory cell to be programmed in first to n-th program states; (S140) Applying the inhibition voltage to the bit line connected to the memory cell to be programmed with a program state corresponding to the first program pulse in the first to n-th program states; (S160) Applying a second program pulse;
Abstract translation: 目的：提供非易失性存储器件及其编程方法，通过在每个程序循环中对每个位线施加禁止电压来减少编程操作中的功耗。 构成：用于对存储器单元进行编程的第一编程脉冲和第二编程脉冲在第一至第n程序状态之间连续地应用一个或多个相应的程序状态。 第一编程脉冲以第一至第n程序状态而不是抑制电压施加到连接到存储单元的位线（S120）。 将抑制电压施加到与要存储单元相连的位线，以与第一编程脉冲相对应的编程状态进行编程（S140）。 应用第二编程脉冲（S160）。 （S120）将第一编程脉冲代替禁止电压施加到与第一〜第n程序状态编程的存储单元连接的位线; （S140）在与第一〜第n程序状态对应的与第一编程脉冲相对应的程序状态下对禁止电压施加到与要存储单元相连的位线; （S160）应用第二个程序脉冲;
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公开(公告)号：KR1020120057284A
公开(公告)日：2012-06-05
申请号：KR1020100118953
申请日：2010-11-26
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/08 , G11C16/10
Abstract: PURPOSE: A nonvolatile memory device, a memory system, and a reading method thereof are provided to improve data reliability by compensating couplings between memory cells. CONSTITUTION: Data stored in a memory cell near a selection memory cell is sensed(S210). The sensed data of the memory cell is temporarily stored. The data stored in the selection memory cell is sensed one or more times by referring to the data of the data stored in the memory cell(S220). The sensed data of the selection memory cell is temporarily stored. The data stored in the memory cell is maintained until another memory cell is sensed to read another selection memory cell(S230).
Abstract translation: 目的：提供非易失性存储器件，存储器系统及其读取方法，以通过补偿存储器单元之间的耦合来提高数据可靠性。 构成：感测存储在选择存储单元附近的存储单元中的数据（S210）。 存储单元的感测数据被暂时存储。 通过参考存储在存储单元中的数据的数据，感测存储在选择存储单元中的数据一次或多次（S220）。 暂时存储选择存储单元的检测数据。 维持存储在存储单元中的数据，直到检测到另一个存储单元读取另一个选择存储单元（S230）。
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Patent Agency Ranking
公开(公告)号：KR1020100011751A
公开(公告)日：2010-02-03
申请号：KR1020080073092
申请日：2008-07-25
Applicant: 삼성전자주식회사
CPC classification number: G11C29/08 , G11C16/04 , G11C2029/0401 , G11C2029/0405 , G11C2029/0409
Abstract: PURPOSE: A test system and a method thereof are provided to rapidly detect a fault on data path by comparing an output data and a test pattern data. CONSTITUTION: A memory device(110) includes a data I/O part. The data I/O part(112) is connected to a data entry path and a data read path. The data entry path is necessary for writing a data in a memory cell array(111). The data read path is necessary for reading a data saved in the memory cell array. A test apparatus(120) compares a output data and a test pattern data of the data I/O part. A test apparatus detects a fault on a data entry path or a data read path.
Abstract translation: 目的：提供一种测试系统及其方法，通过比较输出数据和测试模式数据来快速检测数据路径上的故障。 构成：存储装置（110）包括数据I / O部分。 数据I / O部分（112）连接到数据输入路径和数据读取路径。 数据输入路径对于将数据写入存储单元阵列（111）是必要的。 数据读取路径对于读取保存在存储单元阵列中的数据是必要的。 测试装置（120）比较数据I / O部分的输出数据和测试模式数据。 测试装置检测数据输入路径或数据读取路径上的故障。
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公开(公告)号：KR100866957B1
公开(公告)日：2008-11-05
申请号：KR1020070013338
申请日：2007-02-08
Applicant: 삼성전자주식회사
IPC: G11C16/10
CPC classification number: G11C11/5628
Abstract: 프로그램 시간을 단축시킬 수 있는 불휘발성 메모리 장치 및 그 구동방법이 개시된다. 상기 불휘발성 메모리 장치는 멀티레벨 셀을 구비하며 복수의 데이터 상태들에 대하여 각 상태별로 프로그램 동작을 수행하고, 상기 구동방법은 상기 복수의 데이터 상태들 중 프로그램이 수행될 데이터 상태를 판별하는 단계와, 상기 상태 판별 결과에 따라 동시 프로그램 비트수를 설정하는 단계와, 외부로부터 입력된 데이터에 대하여 스캐닝 동작을 수행함으로써 프로그램이 수행될 데이터들을 검색하는 단계 및 상기 설정된 동시 프로그램 비트수에 따라, 상기 검색단계에서 검색된 데이터들에 대하여 프로그램 동작을 수행하는 단계를 구비한다. 특히 상기 복수의 데이터 상태들 중 적어도 하나의 데이터 상태에 대응하는 동시 프로그램 비트수는, 다른 데이터 상태에 대응하는 동시 프로그램 비트수와 서로 다른 값을 갖도록 설정된다.
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公开(公告)号：KR1020080064063A
公开(公告)日：2008-07-08
申请号：KR1020070000807
申请日：2007-01-03
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3454
Abstract: A method for driving a nonvolatile memory capable of re-verifying a N- time verified memory cell and a nonvolatile memory device are provided to increase accuracy of program for the memory cell by performing additional verification for the verified and programmed memory cell. According to a method for driving a nonvolatile memory capable of re-verifying a N-time verified memory cell, memory cells are programmed on the basis of first data copied to a verify data buffer from a program data buffer(S430). The result of verifying the programmed memory cells is over-written in the verify data buffer(S440). The program step and the verify step are repeated at least one time for the verified memory cells, on the basis of the verify result written in the verify data buffer.
Abstract translation: 提供一种用于驱动能够重新验证N次验证的存储单元和非易失性存储器件的非易失性存储器的方法，以通过对已验证和已编程的存储器单元执行额外的验证来提高存储器单元的程序的精度。 根据用于驱动能够重新验证N次验证的存储单元的非易失性存储器的方法，基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程存储器单元（S430）。 验证编程的存储器单元的结果被重写在验证数据缓冲器中（S440）。 基于写在验证数据缓冲器中的验证结果，针对经验证的存储器单元重复程序步骤和验证步骤至少一次。
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公开(公告)号：KR100648285B1
公开(公告)日：2006-11-23
申请号：KR1020050055225
申请日：2005-06-24
Applicant: 삼성전자주식회사
IPC: G11C16/04
Abstract: An access method and apparatus of a multi level cell flash memory are provided to improve the read speed of a synchronous flash memory using serial sensing, by assembling words of an input/output unit without latching all of one burst unit data. In a flash memory device having memory cells stored with at least 2 bits per cell, a data rearrangement part divides input data of more than two words into a first word and a second word, and stores the first word and the second word in the most significant bits and the least significant bits of the memory cells, respectively, in response to a rearrangement signal. A write driver is controlled for data outputted from the data rearrangement part to be programmed in the memory cells in response to a write enable signal. Multiple sense amplifiers senses the data of the memory cells in response to a sensing enable signal. A latch circuit latches the sensing data of the sense amplifiers in response to a latch control signal. A control part rearranges input data by applying the rearrangement signal, and generates a write enable signal for the rearranged data to be written in the memory cells, and outputs the sensing enable signal to the sense amplifiers to serially sense the most significant bits and the least significant bit of the memory cells during a data read operation, and generates a latch control signal, in order to output the first word when the most significant bits are latched and to output the second word when the least significant bits are latched.
Abstract translation: 提供了一种多级单元闪速存储器的存取方法和装置，通过组合输入/输出单元的字而不锁存一个突发单元数据的全部来提高使用串行感测的同步闪存的读取速度。 在具有以每个单元存储至少2比特的存储单元的闪速存储器件中，数据重新排列部分将多于两个单词的输入数据划分为第一单词和第二单词，并且将第一单词和第二单词存储在最 响应于重新排列信号，分别存储单元的有效位和最低有效位。 响应于写使能信号，对从数据重排部分输出的数据控制写驱动器以在存储单元中编程。 响应于感测使能信号，多个感测放大器感测存储器单元的数据。 锁存电路响应于锁存控制信号而锁存读出放大器的读出数据。 控制部件通过应用重排信号来重新排列输入数据，并且生成用于重排数据的写入使能信号以写入存储器单元中，并且将感测使能信号输出到感测放大器以串行感测最高有效位，并且最少 在数据读操作期间有效位的存储单元，并且产生锁存控制信号，以便当最高有效位被锁存时输出第一个字，并且当最低有效位被锁存时输出第二个字。
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20.发明授权벌크 라인 전압에 따른 프로그램 실행 구간의서스펜드/리쥼 기능을 갖는 불 휘발성 메모리 장치 및그것의 프로그램 방법 失效具有基于大容量电压的程序执行周期的休眠/恢复功能的非易失性存储器件及其程序方法
公开(公告)号：KR100648278B1
公开(公告)日：2006-11-23
申请号：KR1020040089955
申请日：2004-11-05
Applicant: 삼성전자주식회사
IPC: G11C16/12
CPC classification number: G11C16/3459 , G11C16/12
Abstract: 여기에 개시되는 불 휘발성 메모리 장치를 프로그램하는 방법은 프로그램 전압을 선택된 메모리 셀에 공급하는 단계와; 그리고 매 프로그램 구간 동안 프로그램 전압이 검출 전압 이상으로 높아질 때 프로그램 전압의 공급을 일시 중지하는 단계를 포함한다. 매 프로그램 구간에서 프로그램 전압이 검출 전압 이하로 다시 낮아질 때, 프로그램 전압의 공급이 재개된다.
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