公开(公告)号：KR1020080094382A

公开(公告)日：2008-10-23

申请号：KR1020070038761

申请日：2007-04-20

Applicant: 삼성전자주식회사

Inventor： 조범식 ,  한규한

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1009 ,  G11C7/222 ,  G11C2207/105

Abstract: A semiconductor memory device and a driving method thereof are provided to perform stable data masking as being integrated. A memory(100) includes at least one data pin. A memory controller(200) provides data and a masking signal to each data pin. The data and the masking signal are provided serially. The masking signal designates at least one byte or at least one bit among the data, and the designated byte or bit is masked. The memory controller provides the masking signal prior to the data.

Abstract translation: 提供了一种半导体存储器件及其驱动方法，用于执行稳定的数据屏蔽作为集成。 存储器（100）包括至少一个数据引脚。 存储器控制器（200）向每个数据引脚提供数据和屏蔽信号。 数据和屏蔽信号是串行提供的。 掩蔽信号指定数据中的至少一个字节或至少一个位，并且指定的字节或位被掩蔽。 存储器控制器在数据之前提供掩蔽信号。

公开(公告)号：KR1020080044543A

公开(公告)日：2008-05-21

申请号：KR1020060113513

申请日：2006-11-16

Applicant: 삼성전자주식회사

Inventor： 조범식

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

Abstract: A method for compensating skew in a memory device using parallel interface is provided to compensate skew for each data of a number of data lines through per pin data training in an initial mode and through byte data training in a normal operation mode. A memory(120) stores data received through each of a number of data lines in response to a clock signal, or outputs data to each data line in response to the clock signal. A controller(110) performs per pin data training or byte data training for each data of the data lines in response to a control signal. The controller comprises a phase detector(112), a phase control signal generator(114) and a phase shift circuit(116). The phase detector detects a number of skew values corresponding to each data of the data lines by comparing the phase of the clock signal with the phase of the data of each data line. The phase control signal generator outputs a number of first phase control signals corresponding to each skew value in response to the control signal, or outputs a number of second phase control signals corresponding to one skew value. The phase shift circuit shifts the phase of the data of each data line in response to the clock signal, and each of the first phase control signals or each of the second phase control signals.

Abstract translation: 提供了一种用于使用并行接口来补偿存储器件中的偏斜的方法，以通过在初始模式中的每个引脚数据训练和通常的操作模式中的字节数据训练来补偿多个数据线的每个数据的偏移。 存储器（120）响应于时钟信号存储通过多条数据线中的每一条接收的数据，或者响应于时钟信号将数据输出到每条数据线。 响应于控制信号，控制器（110）针对数据线的每个数据执行针脚数据训练或字节数据训练。 控制器包括相位检测器（112），相位控制信号发生器（114）和相移电路（116）。 相位检测器通过将时钟信号的相位与每个数据线的数据的相位相比较来检测与数据线的每个数据相对应的歪斜值的数量。 相位控制信号发生器响应于控制信号输出对应于每个偏斜值的多个第一相位控制信号，或者输出对应于一个歪斜值的多个第二相位控制信号。 相移电路响应于时钟信号和每个第一相位控制信号或每个第二相位控制信号来移动每条数据线的数据的相位。

公开(公告)号：KR1020070121465A

公开(公告)日：2007-12-27

申请号：KR1020060056563

申请日：2006-06-22

Applicant: 삼성전자주식회사

Inventor： 배승준 ,  장성진 ,  조범식

IPC: G06F13/00 ,  G06F1/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A method and a device for compensating de-skew between a data signal and a clock signal in a parallel interface are provided to compensate the de-skew between the data signal and the clock signal in the parallel interface, and reduce a circuit area by combining dede-skew and per-pin de-skew in a CDR mode. A reference clock transmitting block(411) transmits a reference clock signal to a receiving semiconductor(450). N transceiving blocks(421-428) respectively transmit corresponding data by synchronizing a corresponding transmitted sampling clock signal to transceive N-bit parallel data. A per-pin de-skew block(430) individually controls phase of the transmitted sampling clock signal corresponding to the N transceiving blocks based on the de-skew between each bit data of N-bit training data and the reference clock signal in a first mode. The per-pin de-skew block individually controls the phase of the transmitted sampling clock signal corresponding to the N transceiving blocks based on phase de-skew information between one of the N-bit parallel data transmitted to the receiving semiconductor and the reference clock signal in a second mode.

Abstract translation: 提供了用于补偿并行接口中的数据信号和时钟信号之间的去偏移的方法和装置，以补偿并行接口中数据信号与时钟信号之间的去偏移，并且通过组合来减少电路面积 在CDR模式下的dede-skew和每引脚去偏移。 参考时钟发送块（411）将基准时钟信号发送到接收半导体（450）。 N个收发块（421-428）分别通过将相应的发送采样时钟信号同步到收发N位并行数据来发送对应的数据。 每引脚去偏移块（430）基于N位训练数据的每个比特数据和参考时钟信号之间的去偏移来单独地控制与N个收发块相对应的所发送的采样时钟信号的相位，第一 模式。 每引脚去偏移块基于发送到接收半导体的N位并行数据之一和参考时钟信号之间的相位去偏移信息单独地控制与N个收发块相对应的发送采样时钟信号的相位 在第二模式中。

公开(公告)号：KR100604899B1

公开(公告)日：2006-07-28

申请号：KR1020040072470

申请日：2004-09-10

Applicant: 삼성전자주식회사

Inventor： 박철우 ,  김규현 ,  조범식

IPC: G11C5/14

CPC classification number: H03K19/018521 ,  H03K19/00361

Abstract: 누설 전류 감소를 위한 레벨 쉬프팅 회로 및 방법이 개시된다. 상기 레벨 쉬프팅 회로는 출력단과 소스 사이에 직렬 연결된 MOSFET들을 포함하고, VCC 로직 레벨 및 VSS1 로직 레벨을 가지는 입력 신호를 수신하며, 상기 MOSFET들 중 하나에 인가되는 피드백 신호를 이용하여 상기 입력 신호를 VCC 로직 레벨 및 VSS2 로직 레벨을 가지는 신호로 변환하여 상기 변환된 신호를 출력 신호로서 생성하는 로직 회로 및 상기 출력 신호를 이용하여 상기 피드백 신호를 생성하는 피드백 회로를 구비한다.