公开(公告)号：KR1020060085900A

公开(公告)日：2006-07-28

申请号：KR1020050066963

申请日：2005-07-22

Applicant: 삼성전자주식회사

Inventor： 이선정 ,  이수근 ,  신홍재 ,  김태범 ,  서봉석 ,  최승만

IPC: H01L21/28 ,  H01L21/304

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76873 ,  H01L21/76883

Abstract: A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

公开(公告)号：KR1020060012462A

公开(公告)日：2006-02-08

申请号：KR1020040061163

申请日：2004-08-03

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  맹재열 ,  김재학 ,  오일환 ,  신홍재

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/02134 ,  H01L21/3124 ,  H01L21/76826

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO 3/2 )x(HSiO 3/2 )y, wherein x and y satisfy the relationships x+y=1 and 0

公开(公告)号：KR100421055B1

公开(公告)日：2004-03-04

申请号：KR1020020027442

申请日：2002-05-17

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.

Abstract translation: 提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 在具有导电层的半导体衬底上顺序形成阻挡层，层间绝缘层和硬掩模层。 在硬掩模层上形成包括具有第一宽度的第一开口的第一光致抗蚀剂图案。 使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，由此形成具有第一宽度的部分过孔。 第一光致抗蚀剂图案被去除。 将有机材料层涂覆在具有部分通孔的半导体基板上以形成部分通孔以填充有机材料层。 包括与部分通孔对齐的第二开口并具有大于第一宽度的第二宽度的第二光致抗蚀剂图案形成在涂覆的半导体基板上。 使用第二光致抗蚀剂图案作为蚀刻掩模来蚀刻层间绝缘层上的有机材料层和硬掩模层。 第二光致抗蚀剂图案和有机材料层同时被去除。 通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层来形成具有第二宽度的布线区域和具有第一宽度的通孔。

公开(公告)号：KR100421039B1

公开(公告)日：2004-03-03

申请号：KR1020010023751

申请日：2001-05-02

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  이수근

IPC: H01L21/3065

Abstract: PURPOSE: A method and an apparatus for removing a photoresist formed on an interlayer dielectric of a semiconductor device are provided to maintain a dielectric constant of the interlayer dielectric after an ashing process is performed on the photoresist formed on the interlayer dielectric. CONSTITUTION: An interlayer dielectric of a low dielectric constant is formed on a surface of a semiconductor substrate(S1). A photoresist is coated on an upper portion of the interlayer dielectric(S2). A contact hole is formed by patterning the photoresist and the interlayer dielectric(S3). The photoresist is removed by performing an ashing process for the photoresist and the interlayer dielectric is exposed thereby(S4). The interlayer dielectric is contacted with activated hydrogen by performing an activated hydrogen process(S5). A post-process such as a stripping process is performed(S6). The interlayer dielectric is formed by an SiOC:H-based compound. The activated hydrogen includes hydrogen plasma.

Abstract translation: 目的：提供一种去除形成在半导体器件的层间介质上的光刻胶的方法和设备，以在对形成在层间介质上的光刻胶执行灰化处理之后保持层间介质的介电常数。 构成：在半导体基板（S1）的表面形成低介电常数的层间绝缘膜。 光致抗蚀剂被涂覆在层间电介质（S2）的上部。 通过图案化光致抗蚀剂和层间电介质来形成接触孔（S3）。 通过对光致抗蚀剂进行灰化处理来去除光致抗蚀剂，并且由此暴露层间电介质（S4）。 通过执行活化氢过程（S5）使层间电介质与活化氢接触。 执行诸如剥离处理的后处理（S6）。 层间电介质由SiOC：H基化合物形成。 活化的氢包括氢等离子体。

公开(公告)号：KR1020020092681A

公开(公告)日：2002-12-12

申请号：KR1020010031455

申请日：2001-06-05

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a semiconductor device using dual damascene technology is provided to prevent an over-etch of a lower interconnection by using an etch stopping layer composed of an N-doped SiC layer. CONSTITUTION: An etch stopping layer(23) and an interlayer dielectric(26) are sequentially formed on a semiconductor substrate(100) having a lower conductive layer(20). A via hole(30) is formed to expose the etch stopping layer(23) by selectively etching the interlayer dielectric. A second photoresist pattern(32) is formed to expose portions of the interlayer dielectric(26) on the resultant structure. At this time, a photoresist residue(34) is remaining in the via hole. A groove(36) is formed by etching the exposed interlayer dielectric(26) using the second photoresist pattern(32) and the photoresist residue(34) as a mask. After removing the second photoresist pattern(32) and the photoresist residue(34), the surface of the lower conductive layer(20) is exposed by removing the exposed etch stopping layer(23). An N-doped SiC layer is used as the etch stopping layer(23).

Abstract translation: 目的：提供一种使用双镶嵌技术制造半导体器件的方法，以通过使用由N掺杂的SiC层构成的蚀刻停止层来防止下部互连的过度蚀刻。 构成：在具有下导电层（20）的半导体衬底（100）上依次形成蚀刻停止层（23）和层间电介质（26）。 通孔（30）形成为通过选择性地蚀刻层间电介质来露出蚀刻停止层（23）。 形成第二光致抗蚀剂图案（32）以暴露所得结构上的层间电介质（26）的部分。 此时，通孔中残留有光致抗蚀剂残留物（34）。 通过使用第二光致抗蚀剂图案（32）和光致抗蚀剂残留物（34）作为掩模蚀刻暴露的层间电介质（26）来形成凹槽（36）。 在去除第二光致抗蚀剂图案（32）和光致抗蚀剂残留物（34）之后，通过去除暴露的蚀刻停止层（23）来暴露下导电层（20）的表面。 使用N掺杂的SiC层作为蚀刻停止层（23）。

公开(公告)号：KR100351506B1

公开(公告)日：2002-09-05

申请号：KR1020000072089

申请日：2000-11-30

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재

IPC: H01L21/31

公开(公告)号：KR1020020010310A

公开(公告)日：2002-02-04

申请号：KR1020000043961

申请日：2000-07-29

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재 ,  한재현

IPC: H01L21/28

CPC classification number: H01L21/76835 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to control resistant capacitor delay in an interconnection of a high integrated semiconductor device, by forming an interconnection trench of a uniform depth in a low dielectric organic silicon oxide layer. CONSTITUTION: An inorganic silicon oxide layer(13) and an organic silicon oxide layer(15) are sequentially stacked on a substrate(10). A partial trench(17') having the same depth as the organic silicon oxide layer is formed in the organic silicon oxide layer through a patterning process. An oxygen treatment process is performed regarding the surface of the inner wall of the partial trench. A hydrofluoric acid wet etch is performed regarding the partial trench to complete a trench.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，通过在低介电有机氧化硅层中形成均匀深度的互连沟槽来控制高集成半导体器件的互连中的耐电容延迟。 构成：将无机氧化硅层（13）和有机氧化硅层（15）依次层叠在基板（10）上。 通过图案化工艺在有机氧化硅层中形成具有与有机氧化硅层相同的深度的部分沟槽（17'）。 对部分沟槽的内壁的表面进行氧处理。 对部分沟槽进行氢氟酸湿蚀刻以完成沟槽。

公开(公告)号：KR100292403B1

公开(公告)日：2001-07-12

申请号：KR1019970077745

申请日：1997-12-30

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  박희숙 ,  김성진

IPC: H01L21/31

Abstract: PURPOSE: An interlayer dielectric of a semiconductor device and a method for fabricating the same are provided to remove a space between metal lines and perform easily a planarization process by forming an interlayer dielectric having a double structure of a low dielectric layer of a spin coating method and a low dielectric layer of a high density plasma CVD(Chemical Vapor Deposition) method on a semiconductor substrate. CONSTITUTION: A metal layer is formed on a semiconductor substrate(10). A lower metal line(12) is formed by patterning the metal layer. A lower insulating layer(22) is formed thereon. A soft bake process for the lower insulating layer(22) is performed. An upper insulating layer(32') is formed on the semiconductor substrate(10) by using a plasma CVD method. The upper insulating layer is planarized by performing a CMP(Chemical Mechanical Polishing) process.

公开(公告)号：KR1019990025544A

公开(公告)日：1999-04-06

申请号：KR1019970047209

申请日：1997-09-12

Applicant: 삼성전자주식회사

Inventor： 최지현 ,  황병근 ,  신홍재

IPC: H01L27/10

Abstract: 저유전 물질인 HSQ(Hydrogen SilsesQuioxane)를 패시베이션층으로 사용하여 크랙의 발생을 억제하고, 건식식각시 패턴 변형을 억제하며, 우수한 평탄도를 갖는 반도체 집적 회로의 패시베이션층 형성방법에 관하여 개시한다. 이를 위하여 본 발명은 외부 불순물 침투를 방지하는 역할을 하는 질화막 또는 옥시나이트라이드막 으로 구성된 최종 보호막 밑에 탄소 성분을 포함하지 않으며, 고온에서 유동성으로 인한 자체적인 평탄화 특성이 있는 HSQ를 이용한 패시베이션층을 형성한다.

公开(公告)号：KR1019990000811A

公开(公告)日：1999-01-15

申请号：KR1019970023913

申请日：1997-06-10

Applicant: 삼성전자주식회사

Inventor： 최지현 ,  신홍재

IPC: H01L21/28

Abstract: 본 발명은 공동화를 이용한 반도체장치의 금속배선 형성방법에 관해 개시한다. 본 발명은 금속배선으로 사용되는 도전층 패턴사이를 공동화하여 상기 도전층 패턴사이에 형성되는 기생 커패시터의 정전용량을 매우 낮게 한다. 상기 도전층 패턴간의 간격이 좁을 경우에는 그 사이의 영역전체를 공동으로 한정할 수 있고, 상기 도전층 패턴간의 간격이 넓을 경우에는 그 사이의 일부 영역에만 공동을 형성할 수 있다. 이와 같이 도전층 패턴사이를 공동화하는 방식은 기생 커패시터의 정전용량을 낮게 하는 것외에도 공정상 부담을 주지 않는 잇점이 있다.