公开(公告)号：KR1020070109462A

公开(公告)日：2007-11-15

申请号：KR1020060042465

申请日：2006-05-11

Applicant: 재단법인서울대학교산학협력재단

Inventor： 국양 ,  최재혁 ,  정훈휘

IPC: B82B3/00 ,  B82Y40/00

CPC classification number: H01L21/02603 ,  H01L21/02178 ,  H01L21/02554 ,  H01L21/823437

Abstract: A method for growing nanowires is provided to solve both the limitation of conventional vertical transistor manufacture techniques and the limitation of nanowire integration by vertically growing silicon or compound semiconductor nanowires at desired positions on a silicon substrate. A method for growing nanowires includes the steps of: patterning indents at desired positions(101) on a silicon substrate(105); depositing a metal on the bottoms of the indents; depositing an aluminum layer with predetermined thickness on the silicon substrate; subjecting the aluminum layer to anodizing to form an aluminum oxide layer(104) in which cylindrical holes are formed to expose the metal at the desired positions; and growing vertical nanowires through the cylindrical holes.

Abstract translation: 提供了一种用于生长纳米线的方法，以解决常规垂直晶体管制造技术的局限性以及通过在硅衬底上的期望位置垂直生长硅或化合物半导体纳米线来限制纳米线整合。 用于生长纳米线的方法包括以下步骤：在硅衬底（105）上的期望位置（101）上构图凹痕; 在金属底部沉积金属; 在硅衬底上沉积预定厚度的铝层; 对铝层进行阳极氧化以形成氧化铝层（104），其中形成圆柱形孔以将金属暴露在所需位置; 并通过圆柱形孔生长垂直的纳米线。

公开(公告)号：KR100466158B1

公开(公告)日：2005-01-14

申请号：KR1020010072797

申请日：2001-11-21

Applicant: 재단법인서울대학교산학협력재단

Inventor： 국양 ,  서문석

IPC: G02B21/00 ,  G01B21/00 ,  G01N37/00 ,  B82Y20/00

Abstract: PURPOSE: An FET-tip type single/multi cantilever probe and a method for fabricating the same are provided to store and read an electric charge with high-speed, high-precision and high resolution by installing a tip in an FET channel formed on a front end of a cantilever arm. CONSTITUTION: A single FET-tip cantilever probe(100) includes a p-type single crystal silicon-on-insulator substrate(101). A silicon oxide layer(201) and an upper silicon layer(102) are sequentially deposited on the p-type single crystal silicon-on-insulator substrate(101). A cantilever arm(408) is formed by patterning the upper silicon layer(102) extending from a probe body(108) of the single FET-tip cantilever probe(100). A p-type tip(406) is formed in a front end of the cantilever arm(408). The p-type tip(406) is positioned at a center of a channel forming area(503), thereby forming an FET channel having n++-pn++ type structure.

Abstract translation: 目的：提供一种FET尖端型单/多悬臂梁探针及其制造方法，以通过将尖端安装在形成于第一层上的FET沟道中来高速，高​​精度和高分辨率地存储和读取电荷 悬臂的前端。 结构：单个FET尖端悬臂探针（100）包括p型单晶硅绝缘体上硅衬底（101）。 在p型单晶绝缘体上硅衬底（101）上依次淀积氧化硅层（201）和上硅层（102）。 通过图案化从单个FET尖端悬臂探针（100）的探针主体（108）延伸的上硅层（102）形成悬臂（408）。 p型尖端（406）形成在悬臂（408）的前端。 p型尖端（406）位于沟道形成区域（503）的中心，由此形成具有n ++ -pn ++型结构的FET沟道。