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公开(公告)号：KR1019950004860B1
公开(公告)日：1995-05-15
申请号：KR1019920024998
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: The amplifier increases the bit signal magnitude in the word line, and reduces the power consumption of memory core. The amplifier includes a sense amplifier of DRAM cell which prevecns the information destruction by rearrayment of amplifying signal, the 1st interruption transistor(MPL) which electrically isolates an 1/2 Vdd power line from a storage capacitor(CS) by control signal(PL), the 2nd transistor(MTPL) which electrically isolates the storage capacitor(CS) from the sense amplifier, and the 3rd and 4th transistors(MSM,MSN) which electrically connect to the 2nd input terminal(1D) and bit lines(BL,/BL).
Abstract translation: 放大器增加字线中的位信号幅度，并降低存储器内核的功耗。 放大器包括DRAM单元的读出放大器，通过重新放大放大信号来预测信息破坏，第一中断晶体管（MPL）通过控制信号（PL）将1/2 Vdd电源线与存储电容器（CS）电隔离， 将存储电容器（CS）与读出放大器电隔离的第二晶体管（MTPL）以及电连接到第二输入端子（1D）的第三和第四晶体管（MSM，MSN）和位线（BL / BL）。
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公开(公告)号：KR1019940005686B1
公开(公告)日：1994-06-22
申请号：KR1019910006087
申请日：1991-04-16
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: The sense amplifier for use in a dynamic random access memory (DRAM) is disclosed. In a DRAM having a precharging and equalizing circuit for precharging and equalizing first and second bit lines, an NMOS latch connected to a first NMOS transistor of a first conductivity, and a PMOS latch, the sense amplifier includes a second NMOS transistor of a first conductivity having a drain and a source connected between the first NMOS transistor and a ground voltage, and a bipolar transistor having a base connected to a connection node between the first and second NMOS transistors, an emitter (or collector) connected to the ground voltage and a collector (or emitter) connected to a connection node between the first NMOS transistor and the NMOS latch. Thus, a stable limited voltage swing operation is obtained.
Abstract translation: 公开了用于动态随机存取存储器（DRAM）的读出放大器。 在具有用于对第一和第二位线进行预充电和均衡的预充电和均衡电路的DRAM中，连接到具有第一导电性的第一NMOS晶体管和PMOS锁存器的NMOS锁存器，所述读出放大器包括具有第一导电性的第二NMOS晶体管 具有连接在第一NMOS晶体管和接地电压之间的漏极和源极，以及双极晶体管，其基极连接到第一和第二NMOS晶体管之间的连接节点，连接到接地电压的发射极（或集电极）和 集电极（或发射极）连接到第一NMOS晶体管和NMOS锁存器之间的连接节点。 因此，获得稳定的限制电压摆动操作。
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13.发明授权
公开(公告)号：KR1019940003401B1
公开(公告)日：1994-04-21
申请号：KR1019910016458
申请日：1991-09-20
Applicant: 한국전자통신연구원
IPC: G11C11/40
Abstract: COSA for FIFO comprising first and second subarray (Subarray 1, Subarray 2) including a plurality of unit memory cells consisting of writing access transistor (TR1), saving capacitor (C) and reading access transistor (TR5), a plurality of writing beat lines (In0 - In7) and a plurality of writing word lines (WWL-0 - WWL-X) connected to each of said unit memory cells and writing column address selecting line, characterized in that the FIFO memory comprises a plurality of data latches saving data input from said writing beat line by SAN signal which is activated at the same time with the writing column address selecting signal and connected to the beat lines (In0 - In7) and a data drive which drives the data latches by said SAN signal to enable concurrent I/O at the same address.
Abstract translation: 包括由写入存取晶体管（TR1），保存电容器（C）和读取存取晶体管（TR5）组成的多个单元存储单元的第一和第二子阵列（子阵列1，子阵列2）的FIFO的COSA，多个写入脉冲线 （In0-In7）和连接到每个所述单元存储单元并写入列地址选择线的多个写入字线（WWL-0-WWL-X），其特征在于，所述FIFO存储器包括多个数据锁存器来保存数据 通过SAN信号输入来自同时写入列地址选择信号并连接到节拍线（In0-In7）的SAN信号，以及数据驱动器，其通过所述SAN信号驱动数据锁存器以使能并发 同一地址的I / O。
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公开(公告)号：KR1019930006723A
公开(公告)日：1993-04-21
申请号：KR1019910016458
申请日：1991-09-20
Applicant: 한국전자통신연구원
IPC: G11C11/40
Abstract: 본 발명은 FIFO(First-In First- Out)메모리 구조에 관한 것으로 정보손실 없이 동시에 동일 번지에서 읽기/쓰기 동작을 수행하는 COSA(Concurrent I/O Operation at the Same Address)메모리에 관한 것이다.
본발명은 제1및 제2서브러에이(제3도 참조)를 포함하는 FIFO메모리에 있어서, 각각의 비트라인(In0-On7)에 점속되고 쓰기열전번지선택 신호와 동시에 활성화 되는 SAN 신호에 의해 상기 각각의 쓰기비트라인으로 부터 입력되는 데이타를 저장하는 복수의 데이타 래치부(10)들과, 상기 SAN 신호에 의해 상기 데이타 래치부(10)들을 구동시키는 데이타 구동부(20)를 포함하여 제2서브어레이의 1열번지가 쓰기동작을 시작함과 동시에 제1서브어레이의 쓰기워드라인(WWL)이 활성화 되어 동일번지에서 비동기적인 동시 입ㆍ출력 동작이 수행될 수 있다.-
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Patent Agency Ranking
公开(公告)号：KR1019960006380B1
公开(公告)日：1996-05-15
申请号：KR1019930026784
申请日：1993-12-08
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: The sense amplifier amplifies data read in a memory cell by sensing and amplifying a minute voltage difference between a pair of bitlines when the DRAM is driven by a low voltage. The amplifier comprises : 1st/2nd tranasistors(Q1,Q2) equalizing a pair of the bitlines(BIT,BIT_); a 3rd transistor(Q4) controlling the movement of the charge between the bitline(BIT) and a memory cell capacitor(CS); a 4th transistor(Q11) cutting off a plate capacitor(CPL) from a free charge voltage source; a 5th transistor(Q16) receiving a signal(TE) for selecting the bitline(BIT) as a gate node; a 6th transistor(Q17) receiving a signal(TO) for selecting the bitline(BIT_) as a gate node; an amplification means(10) performing a full down sense amplification according to the voltage difference between the bitlines; a 7th transistor(Q12) making the amplication means(10) electrically connected or disconnected to the plate capacitor(CPL).
Abstract translation: 当DRAM由低电压驱动时，感测放大器通过感测和放大一对位线之间的微小电压差来放大存储单元中读取的数据。 放大器包括：均衡一对位线（BIT，BIT_）的第一/第二传导电阻（Q1，Q2）; 控制位线（BIT）和存储单元电容器（CS）之间的电荷移动的第三晶体管（Q4）; 第四晶体管（Q11）从自由充电电压源切断平板电容器（CPL）; 接收用于选择位线（BIT）作为门节点的信号（TE）的第五晶体管（Q16） 接收用于选择位线（BIT_）作为门节点的信号（TO）的第六晶体管（Q17） 放大装置（10），根据所述位线之间的电压差执行全向下感测放大; 第七晶体管（Q12）使得放大装置（10）与平板电容器（CPL）电连接或断开。
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公开(公告)号：KR100088131B1
公开(公告)日：1995-08-19
申请号：KR1019920024998
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G11C11/407
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公开(公告)号：KR1019950010568B1
公开(公告)日：1995-09-19
申请号：KR1019920009679
申请日：1992-06-04
Applicant: 한국전자통신연구원
IPC: G11C11/40
Abstract: The memory array structure of DRAM comprises a first memory array region, a second memory array region, a plurality of bit line pairs connected to the memory cells of the first and second memory array regions, a plurality of word lines, a plurality of sense amplifiers for sensing/amplifying the voltage difference between two bit lines, a plurality of P latches connected between bit line pairs of the first memory array region, a plurality of first equalizers for precharging the bit line pair to 1/2VDD voltage according to a first equalizer signal, a plurality of N latches connected between bit line pairs of the second memory array region, a plurality of second equalizers for precharging the bit line pair to 1/2VDD voltage according to a second equalizer signal, a plurality of barrier transistors for equalizing the bit line voltage of the first and second memory regions according to the pull-up of the first and second control signals or the third and fourth control signals.
Abstract translation: DRAM的存储器阵列结构包括第一存储器阵列区域，第二存储器阵列区域，连接到第一和第二存储器阵列区域的存储器单元的多个位线对，多个字线，多个读出放大器 用于感测/放大两个位线之间的电压差，连接在第一存储器阵列区域的位线对之间的多个P锁存器，用于根据第一均衡器将位线对预充电到1 / 2VDD电压的多个第一均衡器 信号，连接在第二存储器阵列区域的位线对之间的多个N个锁存器，用于根据第二均衡器信号将位线对预充电到1 / 2VDD电压的多个第二均衡器，多个用于均衡 根据第一和第二控制信号或第三和第四控制信号的上拉，第一和第二存储区域的位线电压。
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