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公开(公告)号：KR1019950003394B1
公开(公告)日：1995-04-12
申请号：KR1019920025034
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G11C11/40
Abstract: The DRAM cell array has the triple states of "1" , "0" and "1/2". This array is effective to reduce not only the size of the layout, but also the delay time due to the low inner voltage source. This structure consists of an amplifier that detects and amplifies the voltage difference between two bit lines, transistors of MPL, MTPL, MSM and MSN that are driven by each control sygnals, two arrays that are connected simmetrically, and capacitors, as shown in the figure.
Abstract translation: DRAM单元阵列具有“1”，“0”和“1/2”的三态。 该阵列不仅有效地减少了布局的尺寸，还减少了内部电压低的延迟时间。 该结构包括一个放大器，用于检测和放大两个位线之间的电压差，MPL，MTPL，MSM和MSN的晶体管，由每个控制系统驱动，两个并联连接的阵列和电容器，如图所示 。
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公开(公告)号：KR1019940016241A
公开(公告)日：1994-07-22
申请号：KR1019920024998
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: 본 발명은 DRAM의 감지 동작시 발생하는 미세한 비트선 신호를 4배이상 증가시켜 고집적 DRAM의 안정된 정보감지를 가능하게 하고 감지 동작시 일어나는 비트선 전압스윙을 단일 비트선으로 한정함으로서 기존의 메모리 코어에서 소비되는 전력소비를 약 50% 정도로 감소시키는 고집적 DRAM용 감지 증폭기에 관한 것으로 메모셀 어레이의 저장캐패시터에 연결되는 셀-플레이트(Cell-Plate)선에 2개의 차단 트랜지스터를 채용하여 워드선 구동시 여기되는 비트선 신호를 셀-플레이트선에도 여기시켜 감지증폭기의 두입력(D,/D)사이의 전압 신호차를 감지증폭기에 대하여 약 4배 증대시킨다.
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15.发明授权메가 DRAM용 P.C.P.(PMOS latch Cut-off voltage level Precharge scheme) 감지 증폭기 失效메가DRAM용P.C.P.（PMOS锁存器切断电压电平预充电方案）감지증폭기
公开(公告)号：KR1019920010342B1
公开(公告)日：1992-11-27
申请号：KR1019900002267
申请日：1990-02-23
Applicant: 한국전자통신연구원
IPC: G11C7/06
Abstract: In the P.C.P (PMOS latch cut-off voltage level precharge scheme) sense amplifier for decreasing the size and the interconnection line of mega DRAM, the equalizing signal is applied to the equalizing transistor (Q18) and the precharge driving transistor (Q17). The source and the drain of the equalizing transistor is connected to the bit line and the bit line, respectively. The source and the drain of the precharge driving transistor is connected to the ground and the common source of PMOS latch transistor (Q14,Q15), respectively. The cut-off voltage level of PMOS latch transistor is used in t of precharging.
Abstract translation: 在用于减小大型DRAM的尺寸和互连线的P.C.P（PMOS锁存截止电压电平预充电方案）读出放大器中，均衡信号被施加到均衡晶体管（Q18）和预充电驱动晶体管（Q17）。 均衡晶体管的源极和漏极分别连接到位线和位线。 预充电驱动晶体管的源极和漏极分别连接到接地和PMOS锁存晶体管的公共源（Q14，Q15）。 PMOS锁存晶体管的截止电压电平用于预充电。
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Patent Agency Ranking
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公开(公告)号：KR1019950004860B1
公开(公告)日：1995-05-15
申请号：KR1019920024998
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: The amplifier increases the bit signal magnitude in the word line, and reduces the power consumption of memory core. The amplifier includes a sense amplifier of DRAM cell which prevecns the information destruction by rearrayment of amplifying signal, the 1st interruption transistor(MPL) which electrically isolates an 1/2 Vdd power line from a storage capacitor(CS) by control signal(PL), the 2nd transistor(MTPL) which electrically isolates the storage capacitor(CS) from the sense amplifier, and the 3rd and 4th transistors(MSM,MSN) which electrically connect to the 2nd input terminal(1D) and bit lines(BL,/BL).
Abstract translation: 放大器增加字线中的位信号幅度，并降低存储器内核的功耗。 放大器包括DRAM单元的读出放大器，通过重新放大放大信号来预测信息破坏，第一中断晶体管（MPL）通过控制信号（PL）将1/2 Vdd电源线与存储电容器（CS）电隔离， 将存储电容器（CS）与读出放大器电隔离的第二晶体管（MTPL）以及电连接到第二输入端子（1D）的第三和第四晶体管（MSM，MSN）和位线（BL / BL）。
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公开(公告)号：KR1019940005686B1
公开(公告)日：1994-06-22
申请号：KR1019910006087
申请日：1991-04-16
Applicant: 한국전자통신연구원
IPC: G11C11/407
Abstract: The sense amplifier for use in a dynamic random access memory (DRAM) is disclosed. In a DRAM having a precharging and equalizing circuit for precharging and equalizing first and second bit lines, an NMOS latch connected to a first NMOS transistor of a first conductivity, and a PMOS latch, the sense amplifier includes a second NMOS transistor of a first conductivity having a drain and a source connected between the first NMOS transistor and a ground voltage, and a bipolar transistor having a base connected to a connection node between the first and second NMOS transistors, an emitter (or collector) connected to the ground voltage and a collector (or emitter) connected to a connection node between the first NMOS transistor and the NMOS latch. Thus, a stable limited voltage swing operation is obtained.
Abstract translation: 公开了用于动态随机存取存储器（DRAM）的读出放大器。 在具有用于对第一和第二位线进行预充电和均衡的预充电和均衡电路的DRAM中，连接到具有第一导电性的第一NMOS晶体管和PMOS锁存器的NMOS锁存器，所述读出放大器包括具有第一导电性的第二NMOS晶体管 具有连接在第一NMOS晶体管和接地电压之间的漏极和源极，以及双极晶体管，其基极连接到第一和第二NMOS晶体管之间的连接节点，连接到接地电压的发射极（或集电极）和 集电极（或发射极）连接到第一NMOS晶体管和NMOS锁存器之间的连接节点。 因此，获得稳定的限制电压摆动操作。
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20.发明授权
公开(公告)号：KR1019940003401B1
公开(公告)日：1994-04-21
申请号：KR1019910016458
申请日：1991-09-20
Applicant: 한국전자통신연구원
IPC: G11C11/40
Abstract: COSA for FIFO comprising first and second subarray (Subarray 1, Subarray 2) including a plurality of unit memory cells consisting of writing access transistor (TR1), saving capacitor (C) and reading access transistor (TR5), a plurality of writing beat lines (In0 - In7) and a plurality of writing word lines (WWL-0 - WWL-X) connected to each of said unit memory cells and writing column address selecting line, characterized in that the FIFO memory comprises a plurality of data latches saving data input from said writing beat line by SAN signal which is activated at the same time with the writing column address selecting signal and connected to the beat lines (In0 - In7) and a data drive which drives the data latches by said SAN signal to enable concurrent I/O at the same address.
Abstract translation: 包括由写入存取晶体管（TR1），保存电容器（C）和读取存取晶体管（TR5）组成的多个单元存储单元的第一和第二子阵列（子阵列1，子阵列2）的FIFO的COSA，多个写入脉冲线 （In0-In7）和连接到每个所述单元存储单元并写入列地址选择线的多个写入字线（WWL-0-WWL-X），其特征在于，所述FIFO存储器包括多个数据锁存器来保存数据 通过SAN信号输入来自同时写入列地址选择信号并连接到节拍线（In0-In7）的SAN信号，以及数据驱动器，其通过所述SAN信号驱动数据锁存器以使能并发 同一地址的I / O。
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