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公开(公告)号：KR1020130134618A
公开(公告)日：2013-12-10
申请号：KR1020120058247
申请日：2012-05-31
Applicant: 한국전자통신연구원
IPC: H03K19/173 , G06F17/50
CPC classification number: G06F17/5072 , G06F17/505 , G06F2217/78
Abstract: The present invention relates to an apparatus for reducing peak power using asynchronous circuit design technology comprising: a combinational circuit unit for dividing a combinational circuit into multiple partial circuits based on the depth of input and output; and an asynchronous control circuit unit for asynchronously setting switch operations of the partial circuits according to a temporal relation and controlling the combinational circuit so that the switch operations do not occur in different partial circuits in case the switch operation occurs in one partial circuit. [Reference numerals] (220) Asynchronous control circuit unit;(230,DD,EE,FF) Barrier gate circuit unit;(240,AA,BB,CC) Delay device unit;(250) Proximity circuit unit
Abstract translation: 本发明涉及一种使用异步电路设计技术降低峰值功率的装置，包括：组合电路单元，用于基于输入和输出的深度将组合电路分为多个部分电路; 以及异步控制电路单元，用于根据时间关系异步地设置部分电路的切换操作，并且控制组合电路，使得在一个部分电路中发生开关操作的情况下，在不同的部分电路中不发生开关操作。 （220）异步控制电路单元;（230，DD，EE，FF）阻挡门电路单元;（240，AA，BB，CC）延迟设备单元;（250）接近电路单元
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公开(公告)号：KR1020120072125A
公开(公告)日：2012-07-03
申请号：KR1020100133934
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H03K5/13 , H03K19/173
CPC classification number: G06F17/5027 , G06F17/5059
Abstract: PURPOSE: A delay circuit and an asynchronous circuit simulation apparatus and method in a FPGA(Field Programmable Gate Array) using the same are provided to form a delay circuit by using a look up table within the FPGA. CONSTITUTION: The asynchronous circuit simulation apparatus in a FPGA(Field Programmable Gate Array)(10) includes a control part(300), a function execution part(200), and a delay circuit(100). A plurality of function execution parts is formed according to a plurality of unit functions included in an asynchronous circuit to be simulated. A plurality of delay circuits corresponding to the function execution parts is formed in a proportional to the number of the function execution parts. The control part transmits an input signal requesting a delayed input signal and unit performance function to the delay circuit and the function execution part.
Abstract translation: 目的：提供使用FPGA的FPGA（现场可编程门阵列）中的延迟电路和异步电路仿真装置和方法，以便通过使用FPGA内的查找表形成延迟电路。 构成：FPGA（现场可编程门阵列）（10）中的异步电路仿真装置包括控制部分（300），功能执行部分（200）和延迟电路（100）。 根据包含在待仿真的异步电路中的多个单元功能，形成多个功能执行部。 与功能执行部分的数量成比例地形成与功能执行部分对应的多个延迟电路。 控制部将延迟输入信号和单位性能函数的输入信号发送到延迟电路和功能执行部。
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Patent Agency Ranking
公开(公告)号：KR100934215B1
公开(公告)日：2009-12-29
申请号：KR1020070109206
申请日：2007-10-29
Applicant: 한국전자통신연구원
CPC classification number: G06F9/30003
Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
Abstract translation: 提供了一种基于事件处理指令集的微处理器和使用该微处理器的事件处理方法。 微处理器包括事件寄存器，事件寄存器根据指令集体系结构（ISA）中提供的事件处理指令集和事件控制器将外部产生的事件传送到微处理器中来控制事件。 因此，当被解码为执行程序的指令是事件处理指令时，微处理器可以通过暂停其程序的执行来减少其不必要的功耗，并且还切断其由于中断而导致的不必要的功耗 由于微处理器的程序可以通过在外部事件产生时通过事件寄存器和事件控制器的操作立即重新运行微处理器而被再次执行。
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公开(公告)号：KR101004670B1
公开(公告)日：2011-01-04
申请号：KR1020080120596
申请日：2008-12-01
Applicant: 한국전자통신연구원
Abstract: 본 발명은 파워 게이팅 회로 및 이를 포함하는 반도체 회로에 관한 것으로서, 본 발명의 일면에 반도체 회로는, 전원 전압을 인가받아 입력신호를 처리하고, 처리완료신호를 출력하는 로직 블록과, 로직 블록에 전원 전압을 인가하기 위해 제1 레벨의 요청신호를 제공하고, 요청신호에 대한 응답신호를 입력받으면 제2 레벨의 요청신호를 제공하는 컨트롤러 및 제1 레벨의 요청신호를 제공받아 전원 전압을 로직 블록으로 인가하고, 처리완료신호가 출력되면 응답 신호를 컨트롤러로 제공하고, 제2 레벨의 요청신호를 제공받아 전원 전압을 차단하는 파워 게이팅 회로를 포함하는 것을 특징으로 한다.
파워 게이팅 회로, 반도체 장치-
公开(公告)号：KR1020100060616A
公开(公告)日：2010-06-07
申请号：KR1020080119279
申请日：2008-11-28
Applicant: 한국전자통신연구원
IPC: H04L7/00
CPC classification number: H04L25/4923
Abstract: PURPOSE: A data transmitting device, a data receiving device, a data transmitting system, and a data transmitting method are provided to transmit data by using a data transmitting method unaffected by delay which supports the 2-phase handshake protocol. CONSTITUTION: A data transmitter(100) generates a data signal in a Non-Return-to-Zero form which is classified into the binary value of 0 and the binary value of 1 due to a request signal and the transition point of the request signal. An encoder is applied with the request signal and the data signal. The encoder, by computing the request signal and the data signal, changes the binary value of 0, the binary value of 1, and a current binary value which is equal to the previous binary value, into different current levels.
Abstract translation: 目的：提供数据发送装置，数据接收装置，数据发送系统和数据发送方法，通过使用不受支持二阶段握手协议的延迟影响的数据发送方式来发送数据。 构成：数据发送器（100）以非归零形式生成数据信号，该数据信号由于请求信号和请求信号的转变点而被分类为二进制值0和二进制值1 。 编码器应用请求信号和数据信号。 编码器通过计算请求信号和数据信号，将二进制值0，二进制值1和等于先前二进制值的当前二进制值改变为不同的电流电平。
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公开(公告)号：KR1020090065086A
公开(公告)日：2009-06-22
申请号：KR1020070132526
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: A sensor node based on an event for low power and an operation method thereof are provided to completely remove a clock which largely affects energy consumption of standby time through an asynchronous design method, thereby minimizing energy consumption. An event sensing unit(410) transmits sensing data obtained through request/response events to an event data processing unit(430). An event transceiving unit(420) delivers the received transmitted data to the event data processing unit. The event transceiving unit transmits an event processing result to the outside. The event data processing unit processes the transmitted sensing data and transmission data.
Abstract translation: 提供基于低功率事件的传感器节点及其操作方法，以通过异步设计方法完全去除大大影响待机时间的能量消耗的时钟，从而最小化能量消耗。 事件感测单元（410）将通过请求/响应事件获得的感测数据发送到事件数据处理单元（430）。 事件收发单元（420）将接收到的发送数据传送到事件数据处理单元。 事件收发单元将事件处理结果发送到外部。 事件数据处理单元处理所发送的感测数据和发送数据。
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公开(公告)号：KR1020090043384A
公开(公告)日：2009-05-06
申请号：KR1020070109206
申请日：2007-10-29
Applicant: 한국전자통신연구원
CPC classification number: G06F9/30003
Abstract: 본 발명은 이벤트 처리 명령어 세트에 기반한 마이크로프로세서에 관한 것으로서, 명령어 세트 구조에 구비된 이벤트 처리 명령어 세트에 따라 이벤트를 제어하기 위한 이벤트레지스터와, 외부에서 발생하는 이벤트를 상기 마이크로프로세서 내부로 전달하기 위한 이벤트제어기를 포함하여, 상기 마이크로프로세서가 프로그램의 수행을 위해 해독된 명령어가 이벤트 처리 명령어이면 마이크로프로세서의 동작을 중지함으로써 불필요한 전력 소모를 줄이고, 또한 외부의 이벤트 발생시 상기 이벤트레지스터와 상기 이벤트제어기의 동작에 따라 상기 마이크로프로세서를 즉시 재가동함으로써 정상적인 프로그램 수행을 재개할 수 있어 인터럽트 대기 기간에 소모되는 불필요한 전력 소모를 절감하는 효과가 있다.
ISA, 이벤트 처리 명령어 세트, 마이크로프로세서
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