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    SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION AND METHOD FOR FABRICATING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION AND METHOD FOR FABRICATING THE SAME 审中-公开
    具有通道区域中的重新配置的配置文件的半导体器件及其制造方法

    公开(公告)号：WO2003083951A1

    公开(公告)日：2003-10-09

    申请号：PCT/US2002/041312

    申请日：2002-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

    IPC: H01L29/36

    CPC classification number: H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

    Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

    Abstract translation: 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与传统器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

    DRAIN/SOURCE EXTENSION STRUCTURE OF A FIELD EFFECT TRANSISTOR INCLUDING DOPED HIGH-K SIDEWALL SPACERS
    13.
    发明申请
    DRAIN/SOURCE EXTENSION STRUCTURE OF A FIELD EFFECT TRANSISTOR INCLUDING DOPED HIGH-K SIDEWALL SPACERS 审中-公开
    一个场效应晶体管的漏极/源延伸结构，包括DOPED高K面板间距

    公开(公告)号：WO2004051728A1

    公开(公告)日：2004-06-17

    申请号：PCT/US2003/035355

    申请日：2003-11-06

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： FEUDEL, Thomas ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  KRUEGEL, Stephan

    IPC: H01L21/336

    CPC classification number: H01L29/6659 ,  H01L21/2253 ,  H01L29/665 ,  H01L29/7833

    Abstract: High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

    Abstract translation: 场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度 。 以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管性能。

    SOI FIELD EFFECT TRANSISTOR ELEMENT HAVING A RECOMBINATION REGION AND METHOD OF FORMING SAME
    15.
    发明申请
    SOI FIELD EFFECT TRANSISTOR ELEMENT HAVING A RECOMBINATION REGION AND METHOD OF FORMING SAME 审中-公开
    具有重组区的SOI场效应晶体管元件及其形成方法

    公开(公告)号：WO2004004015A2

    公开(公告)日：2004-01-08

    申请号：PCT/US2003/020791

    申请日：2003-06-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  KRUEGER, Christian

    IPC: H01L29/786

    CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78684

    Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer 320 is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

    Abstract translation: 公开了一种SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包括具有轻微晶格失配的区域来产生高浓度的固定点缺陷。 在一个特定实施例中，由于在热处理晶体管元件时松弛硅锗层的应变，所以在具有高浓度点缺陷的有源区中提供硅锗层320。 由于点缺陷，重组率显着增加，从而减少了存储在有源区域中的带电载流子的数量。

    METHOD OF FORMING DIFFERENT SILICIDE PORTIONS ON DIFFERENT SILICON-CONTAINING REGIONS IN A SEMICONDUCTOR DEVICE
    16.
    发明申请
    METHOD OF FORMING DIFFERENT SILICIDE PORTIONS ON DIFFERENT SILICON-CONTAINING REGIONS IN A SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件中形成不同含硅区域的不同硅化物部分的方法

    公开(公告)号：WO2003075330A1

    公开(公告)日：2003-09-12

    申请号：PCT/US2002/041660

    申请日：2002-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

    IPC: H01L21/285

    CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/665

    Abstract: A method is disclosed in which different metal layers (240, 242) are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers (240, 242) may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions (241, 243) may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions (241, 243), wherein at least one silicide portion comprises noble metal.

    Abstract translation: 公开了一种方法，其中不同的金属层240,242依次沉积在含硅区域上，使得金属层240,242的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成硅化物部分241,243，该硅化物部分241,243分别适应于特定的含硅区域，从而可以显着提高各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分241,243的含硅区域，其中至少一个硅化物部分包括贵金属。

    METHOD OF FORMING A NICKEL SILICIDE REGION IN A DOPED SILICON-CONTAINING SEMICONDUCTOR AREA
    20.
    发明申请
    METHOD OF FORMING A NICKEL SILICIDE REGION IN A DOPED SILICON-CONTAINING SEMICONDUCTOR AREA 审中-公开
    在含硅含硅半导体区域形成镍硅酸盐区域的方法

    公开(公告)号：WO2004042809A1

    公开(公告)日：2004-05-21

    申请号：PCT/US2003/033965

    申请日：2003-10-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  LENSKI, Markus

    IPC: H01L21/285

    CPC classification number: H01L21/28518 ,  H01L21/26506

    Abstract: In highly sophisticated MOS transistors including nickel silicide portions (311) for reducing the silicon sheet resistance, nickel silicide stingers may lead to short circuits between the drain and source region and the channel region, thereby significantly lowering production yield. By substantially amorphizing corresponding portions (331) of the source and drain regions, the creation of clustered point defects may effectively be avoided during curing implantation induced damage, wherein a main diffusion path for nickel during the nickel silicide formation is interrupted. Thus, nickel silicide stingers may be significantly reduced or even completely avoided.

    Abstract translation: 在包括用于降低硅片电阻的硅化镍部分（311）的高度复杂的MOS晶体管中，硅化镍烙铁可能导致漏极和源极区域和沟道区域之间的短路，从而显着降低产量。 通过使源极和漏极区域的对应部分（331）基本非晶化，可以在固化植入诱导的损伤期间有效地避免产生聚集点缺陷，其中在镍硅化物形成期间镍的主扩散路径被中断。 因此，可以显着降低或甚至完全避免硅化镍刺痛。

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