公开(公告)号：EP1226586B1

公开(公告)日：2003-06-18

申请号：EP00967094.4

申请日：2000-09-29

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： YAMADA, Shigekasu ,  BILL, Colin, S. ,  VANBUSKIRK, Michael, A.

IPC: G11C16/28 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/14

Abstract: A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line (422) operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line (421) operatively connected between an output of a boosting circuit and the sector wordline of the "far" sector. As a consequence, the reference wordlines voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.

公开(公告)号：EP1264315A2

公开(公告)日：2002-12-11

申请号：EP01920327.2

申请日：2001-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PAN, Feng ,  BILL, Colin, S.

IPC: G11C29/00 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3454

Abstract: A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch (14) is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch (16) is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator (18) is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.

公开(公告)号：EP1559110A1

公开(公告)日：2005-08-03

申请号：EP03810746.2

申请日：2003-07-10

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： VANBUSKIRK, Michael, A. ,  FANG, Tzu-Ning ,  BILL, Colin, S. ,  LAN, Zhida

IPC: G11C16/02 ,  G11C13/02

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array (100, 200, 212, 300, 400). State change voltages can be applied to a single device in the array (100, 200, 212, 300, 400) of semiconductor devices without the need for transistor-type voltage controls. The diodic effect (114, 508, 510, 900, 1014, 1114, 1214, 1502, 1702, 1812) of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

公开(公告)号：EP1529293A1

公开(公告)日：2005-05-11

申请号：EP03765441.5

申请日：2003-06-10

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BILL, Colin, S. ,  HALIM, Azrul ,  HAMILTON, Darlene ,  BAUTISTA, Edward, V., Jr. ,  LEE, Weng, Fook ,  CHEAH, Ken, Cheong ,  LAW, Chee, Boon ,  TEH, Boon, Tang ,  KUCERA, Joseph ,  SALLEH, Syahrizal

IPC: G11C29/00

CPC classification number: G11C29/72 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

Abstract: In a BIST (built-in-self-test) system (300) for testing flash memory cells (304) fabricated on a semiconductor substrate (302), a BIST (built-in-self-test) interface (312), a front-end state machine (314), and a back-end state machine (316) are fabricated on the semiconductor substrate (302). The BIST interface (312) inputs test mode data from an external test system (318), and the front-end state machine (314) decodes the test mode data to determine an order for performing at least one desired test mode. The back-end state machine (316) performs the at least one desired test mode on the flash memory cells (304) according to the order for on-­chip testing of the flash memory cells (304).

公开(公告)号：EP1266382B1

公开(公告)日：2004-01-02

申请号：EP01910464.5

申请日：2001-02-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BILL, Colin, S. ,  GUTALA, Ravi, P.

IPC: G11C16/08 ,  G11C8/00 ,  G11C5/14

CPC classification number: G11C16/08 ,  G11C5/145 ,  G11C8/08

Abstract: A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory (10) is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster (48) in a wordline voltage booster circuit (20). An adjustable clamp circuit (12) is electrically connected with the wordline voltage booster circuit (20) for clamping the gate voltage that is generated by the voltage booster (48) at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit (14) that is electrically connected to the adjustable clamp circuit (12), depending on process variations experienced during fabrication by the adjustable clamp circuit (12).

公开(公告)号：EP1529293B1

公开(公告)日：2005-11-23

申请号：EP03765441.5

申请日：2003-06-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BILL, Colin, S. ,  HALIM, Azrul ,  HAMILTON, Darlene ,  BAUTISTA, Edward, V., Jr. ,  LEE, Weng, Fook ,  CHEAH, Ken, Cheong ,  LAW, Chee, Boon ,  TEH, Boon, Tang ,  KUCERA, Joseph ,  SALLEH, Syahrizal

IPC: G11C29/00

CPC classification number: G11C29/72 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

公开(公告)号：EP1116240B1

公开(公告)日：2002-11-13

申请号：EP99949746.4

申请日：1999-09-21

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： BILL, Colin, S. ,  SU, Jonathan, S. ,  AKAOGI, Takao ,  GUTALA, Ravi, P.

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) (10) includes a plurality of floating gate transistor memory cells (32), a plurality of wordlines (WL) connected to the cells (32) and a power source (13) for generating a low power supply voltage on the order of 3 V or less. A wordline driver (50) includes a booster (52) for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp (54) limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp (54) can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp (56) limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the begining of the read operation to ensure that the cells (32) have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

公开(公告)号：EP1116240A1

公开(公告)日：2001-07-18

申请号：EP99949746.4

申请日：1999-09-21

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： BILL, Colin, S. ,  SU, Jonathan, S. ,  AKAOGI, Takao ,  GUTALA, Ravi, P.

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) (10) includes a plurality of floating gate transistor memory cells (32), a plurality of wordlines (WL) connected to the cells (32) and a power source (13) for generating a low power supply voltage on the order of 3 V or less. A wordline driver (50) includes a booster (52) for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp (54) limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp (54) can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp (56) limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the begining of the read operation to ensure that the cells (32) have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

公开(公告)号：EP1258007B1

公开(公告)日：2003-10-22

申请号：EP01908956.4

申请日：2001-02-07

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： YAMADA, Shigekazu ,  AKAOGI, Takao ,  BILL, Colin, S.

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines (18) during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit (16) to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit (16) is activated by an activation circuit (12) when the read operation is initiated. During the read operation, the wordline driver circuit (16) maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit (16).

公开(公告)号：EP1256116B1

公开(公告)日：2003-09-03

申请号：EP00948688.7

申请日：2000-07-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BILL, Colin, S. ,  SU, Johathan, Shi-Chang ,  GUTALA, Ravi, P.

IPC: G11C8/00 ,  G11C16/08

CPC classification number: G11C8/12 ,  G11C8/10

Abstract: The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.