公开(公告)号：DE69933600D1

公开(公告)日：2006-11-30

申请号：DE69933600

申请日：1999-02-25

Applicant: ALTERA CORP

Inventor： TURNER JOHN ,  MEJIA MANUEL

IPC: G11C11/41 ,  G11C11/412 ,  G11C5/00 ,  G11C7/00 ,  G11C19/00

公开(公告)号：DE60144544D1

公开(公告)日：2011-06-09

申请号：DE60144544

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/02 ,  H04L7/04 ,  G06F1/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/033

公开(公告)号：DE60137324D1

公开(公告)日：2009-02-26

申请号：DE60137324

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/02 ,  H04L7/04 ,  G06F1/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/033

Abstract: A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ('LVDS'). The circuitry may be part of a larger system.