公开(公告)号：AU2011203640A1

公开(公告)日：2012-08-02

申请号：AU2011203640

申请日：2011-01-05

Applicant: APPLE INC

Inventor： BRATT JOSEPH P ,  CHOO SHING HORNG ,  HOLLAND PETER F ,  MILLET TIMOTHY J

IPC: G06F3/14 ,  H04N5/265

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

公开(公告)号：GB2479452A

公开(公告)日：2011-10-12

申请号：GB201105852

申请日：2011-04-07

Applicant: APPLE INC

Inventor： CESARE JOSH P DE ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/32

Abstract: Automatically transitioning the performance states of components in an integrated circuit comprises a plurality of performance domains each including at least one component, and a power management unit (PMU). The PMU is configured to transition 44 at least one performance domain to a first performance state in response to a processor transitioning 40 to a different performance state (such as low performance or sleep state). The PMU may further transition the performance domain to a second performance state 52 in response to the processor exiting 48 the low performance state. The apparatus may include registers that can be programmed with the one or more performance states of the performance domains and the processor. Timestamps may be recorded 48, 54 at the time of performance domains transition. A performance state may include any combination of performance characteristics for the relevant components, such as a different operating frequency of the provided clock signal and a corresponding supply voltage.

公开(公告)号：AU2014349166B2

公开(公告)日：2017-02-16

申请号：AU2014349166

申请日：2014-09-29

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  GULATI MANU ,  CULBERT MICHAEL F

IPC: G06F3/16 ,  G06F1/32 ,  G10L15/22

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：AU2011292290B2

公开(公告)日：2014-07-10

申请号：AU2011292290

申请日：2011-08-11

Applicant: APPLE INC

Inventor： COTE GUY ,  FREDERIKSEN JEFFREY E ,  BRATT JOSEPH P ,  GO SHUN WAI ,  MILLET TIMOTHY J

IPC: H04N5/232

Abstract: Various techniques are provided for processing image data acquired using a digital image sensor 90. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system 10 that supports multiple image sensors 90. In one embodiment, the image processing system 32 may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit 80 from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors 90a, 90b are provided to the front-end pixel processing unit 80 in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors 90a, 90b are written to a memory 108, and then read out to the front-end pixel processing unit 80 in an interleaved manner.

公开(公告)号：AU2011203640B2

公开(公告)日：2014-01-09

申请号：AU2011203640

申请日：2011-01-05

Applicant: APPLE INC

Inventor： BRATT JOSEPH P ,  CHOO SHING HORNG ,  HOLLAND PETER F ,  MILLET TIMOTHY J

IPC: G06F3/14 ,  H04N5/265

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

公开(公告)号：MX2013001921A

公开(公告)日：2013-05-20

申请号：MX2013001921

申请日：2011-08-11

Applicant: APPLE INC

Inventor： COTE GUY ,  FREDERIKSEN JEFFREY E ,  BRATT JOSEPH P ,  GO SHUN WAI ,  MILLET TIMOTHY J

IPC: H04N5/232

Abstract: Se proporcionan varias técnicas para procesar datos de imagen adquiridos utilizando un sensor de imágenes digitales 90; de acuerdo con aspectos de la presente divulgación, una de esas técnicas se puede referir al procesamiento de datos de imagen en un sistema 10 que soporta múltiples sensores de imagen 90; en una modalidad, el sistema de procesamiento de imágenes 32 puede incluir circuitería de control configurada para determinar si un dispositivo está operando en un modo de sensor sencillo (un sensor activo) o un modo de sensor dual (dos sensores activos); cuando opera en el modo de sensor sencillo, los datos pueden ser proporcionados directamente a una unidad de procesamiento de píxel de etapa inicial 80 desde la interfaz de sensor del sensor activo; cuando opera en un modo de sensor dual, los cuadros de imagen del primer y segundo sensores 90a, 90b son proporcionados a la unidad de procesamiento de píxel de etapa inicial 80 en una manera intercalada; por ejemplo, en una modalidad, los cuadros de imagen del primer y segundo sensores 90a, 90b son escritos en una memoria 108, y después leídos en la unidad de procesamiento de pixel de etapa inicial 80 en una manera intercalada

公开(公告)号：GB2484204B

公开(公告)日：2013-02-13

申请号：GB201116886

申请日：2011-09-30

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIK P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32 ,  G06F9/44 ,  G06F12/08

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：GB2479452B

公开(公告)日：2012-07-18

申请号：GB201105852

申请日：2011-04-07

Applicant: APPLE INC

Inventor： CESARE JOSH P DE ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/32

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU maybe programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

公开(公告)号：WO2011006096A3

公开(公告)日：2011-04-07

申请号：PCT/US2010041570

申请日：2010-07-09

Applicant: APPLE INC ,  WANG JAMES ,  CHEN ZONGJIAN ,  KELLER JAMES B ,  MILLET TIMOTHY J

Inventor： WANG JAMES ,  CHEN ZONGJIAN ,  KELLER JAMES B ,  MILLET TIMOTHY J

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F12/08 ,  G06F2212/2515 ,  Y02D10/13

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract translation: 在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。 控制电路可以将非透明存储器作为一组非透明存储器块进行管理。 在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。 控制电路可以分配第一块，并且可以返回所分配的块的地址（或其他指示），使得软件可以访问块。 控制电路还可以在非透明存储器与非透明存储器单元耦合到的主存储器系统之间提供自动数据移动。 例如，自动数据移动可以包括在分配的块的处理完成之后从主存储器系统填充数据到所分配的块，或者将分配的块中的数据刷新到主存储器系统。

公开(公告)号：DE112016003527T5

公开(公告)日：2020-05-20

申请号：DE112016003527

申请日：2016-06-09

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  GULATI MANU ,  SPENCE ARTHUR L ,  SAUND GURJEET S ,  ESSER ROBERT P

IPC: G06F9/48

Abstract: Eine Ausführungsform eines Systems kann eine Mehrzahl von Medieneinheiten, einen Prozessor und Schaltlogik einschließen. Jede Medieneinheit kann konfiguriert sein, einen oder mehrere Befehle auszuführen, um ein Anzeigebild zu verarbeiten. Der Prozessor kann konfiguriert sein, eine Mehrzahl von Medienverarbeitungsbefehlen in einer Warteschlange zu speichern. Die Schaltlogik kann konfiguriert sein einen ersten Medienverarbeitungsbefehl aus der Warteschlange abzurufen und den ersten Medienverarbeitungsbefehl an eine erste Medieneinheit zu senden. Die Schaltlogik kann zudem konfiguriert sein, eine zweite Medienverarbeitung aus der Warteschlange abzurufen und als Reaktion auf ein Empfangen eines Interrupts von der ersten Medieneinheit kommend den zweiten Medienverarbeitungsbefehl an eine zweite Medieneinheit zu senden. Die Schaltlogik kann dann als Reaktion auf das Empfangen des Interrupts von der ersten Medieneinheit kommend Daten von der ersten Medieneinheit zur zweiten Medieneinheit kopieren.