公开(公告)号：BR112013013300A2

公开(公告)日：2016-09-13

申请号：BR112013013300

申请日：2011-11-17

Applicant: APPLE INC

Inventor： MACHNICKI ERIK P ,  CESARE JOSH P DE ,  HAYTER MARK D ,  WADHAWAN RUCHI

IPC: G06F13/24

公开(公告)号：GB2479452A

公开(公告)日：2011-10-12

申请号：GB201105852

申请日：2011-04-07

Applicant: APPLE INC

Inventor： CESARE JOSH P DE ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/32

Abstract: Automatically transitioning the performance states of components in an integrated circuit comprises a plurality of performance domains each including at least one component, and a power management unit (PMU). The PMU is configured to transition 44 at least one performance domain to a first performance state in response to a processor transitioning 40 to a different performance state (such as low performance or sleep state). The PMU may further transition the performance domain to a second performance state 52 in response to the processor exiting 48 the low performance state. The apparatus may include registers that can be programmed with the one or more performance states of the performance domains and the processor. Timestamps may be recorded 48, 54 at the time of performance domains transition. A performance state may include any combination of performance characteristics for the relevant components, such as a different operating frequency of the provided clock signal and a corresponding supply voltage.

公开(公告)号：GB2479452B

公开(公告)日：2012-07-18

申请号：GB201105852

申请日：2011-04-07

Applicant: APPLE INC

Inventor： CESARE JOSH P DE ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/32

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU maybe programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.