公开(公告)号：WO2013081715A1

公开(公告)日：2013-06-06

申请号：PCT/US2012/055429

申请日：2012-09-14

Applicant: APPLE INC. ,  TRIPATHI, Brijesh ,  BHARGAVA, Nitin ,  OKRUHLICA, Craig, M.

Inventor： TRIPATHI, Brijesh ,  BHARGAVA, Nitin ,  OKRUHLICA, Craig, M.

IPC: G09G5/00

CPC classification number: G06T3/606 ,  G09G5/393 ,  G09G2340/0492 ,  G09G2360/122

Abstract: Methods and apparatus for performing an inline rotation of an image. The apparatus includes a rotation unit for reading pixels from a source image in an order based on a specified rotation to be performed. The source image is partitioned into multiple tiles, the tiles are processed based on where they will be located within the rotated image, and each tile is stored in a tile buffer. The target pixel addresses within a tile buffer are calculated and stored in a lookup table, and when the pixels are retrieved from the source image by the rotation unit, the lookup table is read to determine where to write the pixels within a corresponding tile buffer.

Abstract translation: 执行图像的在线旋转的方法和装置。 该装置包括旋转单元，用于基于要执行的指定旋转以顺序从源图像读取像素。 源图像被分割成多个图块，基于它们将位于旋转图像内的位置对图块进行处理，并且每个图块被存储在平铺缓冲器中。 计算瓦片缓冲器内的目标像素地址并将其存储在查找表中，并且当通过旋转单元从源图像检索像素时，读取查找表以确定在相应的瓦片缓冲器内写入像素的位置。

公开(公告)号：WO2016190955A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/025048

申请日：2016-03-30

Applicant: APPLE INC.

Inventor： WANG, Chaohao ,  TRIPATHI, Brijesh ,  TANN, Christopher, Philip Alan ,  ZALATIMO, David, S. ,  COTE, Guy ,  NAN, Hao ,  ALBRECHT, Marc ,  SACCHETTO, Paolo ,  PINTZ, Sandro, H.

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G2320/0204 ,  G09G2320/0247 ,  G09G2320/0257 ,  G09G2320/046 ,  G09G2340/0435 ,  G09G2360/16

Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.

Abstract translation: 电子设备可以生成要显示在显示器上的内容。 显示器可以具有用于显示内容的图像帧的液晶显示像素阵列。 图像帧可以以正极性和负极性显示，以帮助减少电荷积累效应。 电荷累积跟踪器可以分析图像帧以确定何时存在电荷累积过多的风险。 电荷累积跟踪器可以分析关于灰度级，帧持续时间和帧极性的信息。 电荷累积跟踪器可以计算整个图像帧的电荷累积度量，或者可以分别处理每个帧的子区域。 当分区域被单独处理时，可以对每个子区域进行单独的监视，以获得过剩电荷累积的风险。

公开(公告)号：WO2015187246A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/024653

申请日：2015-04-07

Applicant: APPLE INC.

Inventor： SMITH, Michael, J. ,  DE CESARE, Josh, P. ,  TRIPATHI, Brijesh ,  IWAMOTO, Derek ,  KEIL, Shane, J.

IPC: G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器（FIFO）和第二FIFO。 第一FIFO被耦合以从接入端口接收数据，并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO，并且该信息随后可以由IC中的功能单元读取。 类似地，功能单元可以将信息写入第二FIFO，随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此，即使在IC中没有实现用于该接口的物理连接和支持电路，也可以模拟特定类型的接口。

公开(公告)号：WO2013130220A1

公开(公告)日：2013-09-06

申请号：PCT/US2013/024603

申请日：2013-02-04

Applicant: APPLE INC.

Inventor： SHARMA, Anup K. ,  KRUEGER, Scott P. ,  HOLLABAUGH, James M. ,  YEPEZ, Roberto G. ,  ADLER, Mitchell D. ,  TRIPATHI, Brijesh ,  TERLIZZI, Jeffrey J. ,  TIKALSKY, Terry L.

IPC: G06F3/14

CPC classification number: G06F3/1431 ,  G06F3/14 ,  G06F13/385 ,  G06F13/4013 ,  G06F13/4018 ,  G06T1/60 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a host computing device (10) includes an internal display (12) and also includes a connector (18) to connect to an external display (16). A cable (14) is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities (24). For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

Abstract translation: 在一个实施例中，主计算设备（10）包括内部显示器（12），并且还包括连接到外部显示器（16）的连接器（18）。 提供电缆（14）以连接到连接器并连接到外部显示器。 电缆包括视频处理能力（24）。 例如，电缆可以包括被配置为存储帧缓冲器的存储器。 帧缓冲器可以存储视频数据的帧，以供视频处理设备在电缆中进一步处理。 视频处理设备可以以各种方式操纵帧，例如， 缩放，旋转，伽马校正，抖动校正等

公开(公告)号：WO2013126242A1

公开(公告)日：2013-08-29

申请号：PCT/US2013/025743

申请日：2013-02-12

Applicant: APPLE INC.

Inventor： OKRUHLICA, Craig M. ,  TRIPATHI, Brijesh ,  BHARGAVA, Nitin

IPC: G06T15/50 ,  G09G5/36 ,  G06T15/00 ,  G06F1/32

CPC classification number: G09G5/363 ,  G06F1/325 ,  G06T1/20 ,  G06T17/00 ,  G06T2210/32 ,  G09G2330/021 ,  G09G2340/10

Abstract: A graphics processing circuit and method for power savings in the same is disclosed. In one embodiment, a graphics processing circuit includes a number of channels. The number of channels includes a number of color component channels that are each configured to process color components of pixel values of an incoming frame of graphics information. The number of channels also includes an alpha scaling channel configured to process alpha values (indicative of a level of transparency) for the incoming and/or outgoing frames. The graphics processing circuit also includes a control circuit. The control circuit is configured to place the alpha scaling channel into a low-power state responsive to determining that at least one of the incoming or outgoing frames does not include alpha values.

Abstract translation: 公开了一种图形处理电路及其省电方法。 在一个实施例中，图形处理电路包括多个通道。 通道数量包括多个颜色分量通道，每个颜色分量通道被配置为处理进入的图形信息帧的像素值的颜色分量。 频道数量还包括被配置为处理传入和/或输出帧的alpha值（指示透明度水平）的α缩放通道。 图形处理电路还包括控制电路。 控制电路被配置为响应于确定进入或输出帧中的至少一个不包括阿尔法值将阿尔法缩放通道置于低功率状态。

公开(公告)号：WO2012099727A1

公开(公告)日：2012-07-26

申请号：PCT/US2012/020507

申请日：2012-01-06

Applicant: APPLE INC. ,  SAUND, Gurjeet S. ,  BISWAS, Sukalpa ,  TRIPATHI, Brijesh

Inventor： SAUND, Gurjeet S. ,  BISWAS, Sukalpa ,  TRIPATHI, Brijesh

IPC: H04W4/00

CPC classification number: H04L49/356 ,  H04L49/354

Abstract: In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

Abstract translation: 在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件控制通信的各个方面。 在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。 在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

公开(公告)号：WO2017052993A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048864

申请日：2016-08-26

Applicant: APPLE INC. ,  TRIPATHI, Brijesh

Inventor： TRIPATHI, Brijesh ,  TANN, Christopher P. ,  WANG, Chaohao ,  ZALATIMO, David S. ,  COTE, Guy

IPC: G09G3/20

CPC classification number: G09G3/3614 ,  G09G3/20 ,  G09G2310/0256 ,  G09G2310/08 ,  G09G2320/0204 ,  G09G2330/021 ,  G09G2340/0435

Abstract: Devices and methods for reducing and/or substantially eliminating pixel charge imbalance due to variable refresh rates are provided. By way of example, a method includes providing a first frame of image data via a processor to a plurality of pixels of the display during a first frame period corresponding to a first refresh rate, and providing a second frame of image data to the plurality of pixels of the display during a second frame period corresponding to a second refresh rate. The method further includes dividing the first frame period into a first frame sub-period and a second frame sub-period, and driving the plurality of pixels of the display with the first frame of image data during the first frame sub-period and the second frame sub-period.

Abstract translation: 提供了用于减少和/或基本消除由于可变刷新率引起的像素电荷不平衡的装置和方法。 作为示例，一种方法包括：在对应于第一刷新率的第一帧周期期间，通过处理器向显示器的多个像素提供图像数据的第一帧，以及向第一帧提供图像数据的第二帧， 在第二帧周期期间对应于第二刷新率的显示器的像素。 该方法还包括将第一帧周期划分为第一帧子周期和第二帧子周期，并且在第一帧子周期期间以第一帧图像数据驱动显示器的多个像素，并且第二帧周期 帧分期。

公开(公告)号：WO2015183377A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/020330

申请日：2015-03-13

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik, P. ,  HERBECK, Gilbert, H. ,  MILLET, Timothy, J. ,  DE CESARE, Joshua, P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：WO2014160588A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/031343

申请日：2014-03-20

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  HOLLAND, Peter F. ,  KUO, Albert C.

IPC: G06F3/14 ,  G09G5/393 ,  G09G5/395

CPC classification number: G09G5/395 ,  G06F3/14 ,  G09G5/001 ,  G09G5/393 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为压缩输出帧并且响应于检测到输出帧中的静态内容而将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。

公开(公告)号：WO2014160574A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/031226

申请日：2014-03-19

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  HOLLAND, Peter F. ,  KUO, Albert C.

IPC: G06F3/14 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06T1/60 ,  G06F3/14 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为压缩输出帧并且响应于检测到输出帧中的静态内容而将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。