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    12.
    发明专利
    未知

    公开(公告)号：DE2908316A1

    公开(公告)日：1979-09-06

    申请号：DE2908316

    申请日：1979-03-03

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMER ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

    IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00 ,  G06F9/00 ,  H03K19/00 ,  H04L11/00

    Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

    14.
    发明专利
    未知

    公开(公告)号：IT1111606B

    公开(公告)日：1986-01-13

    申请号：IT6744778

    申请日：1978-03-03

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMER ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

    IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  G06F

    Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

    16.
    发明专利
    未知

    公开(公告)号：IT1082756B

    公开(公告)日：1985-05-21

    申请号：IT6770277

    申请日：1977-03-31

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BARCAROLI VALERIO ,  DEMICHELIS CARLO ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO

    IPC: H04Q3/545 ,  H04M

    Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus-if the latter is available-whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.

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