-
公开(公告)号：ITTO940462A1
公开(公告)日：1995-12-06
申请号：ITTO940462
申请日：1994-06-06
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA WALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
-
公开(公告)号：CA2203489C
公开(公告)日：2001-07-10
申请号：CA2203489
申请日：1997-04-23
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , PESANDO LUCA
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H01S3/10
Abstract: A high speed drive circuit for optical sources. The circuit comprises bias and modulation current generators for both p-type and n-type optical sources, and a pair of control voltage sources for controlling the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. The circuit includes control logic and CMOS gates for selecting between the p-type and n-type generators by means of an external signal. The circuit is fabricated as an integrated circuit having three pads, one for each control voltage source and the third pad comprises the current generators, the CMOS gates and the control logic circuit.
-
公开(公告)号：IT1285852B1
公开(公告)日：1998-06-24
申请号：ITTO960326
申请日：1996-04-24
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , PESANDO LUCA
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152
Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).
-
公开(公告)号：ITTO960665A1
公开(公告)日：1998-02-02
申请号：ITTO960665
申请日：1996-07-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO
-
15.发明专利
公开(公告)号：CA2212292A1
公开(公告)日：1998-01-31
申请号：CA2212292
申请日：1997-07-30
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： PELLEGRINO PAOLO , BOSTICA BRUNO , BURZIO MARCO
Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.
-
Patent Agency Ranking
公开(公告)号：ITTO960326A1
公开(公告)日：1997-10-24
申请号：ITTO960326
申请日：1996-04-24
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , PESANDO LUCA
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152
Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).
-
公开(公告)号：CA2190069A1
公开(公告)日：1997-05-14
申请号：CA2190069
申请日：1996-11-12
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： PELLEGRINO PAOLO , BURZIO MARCO
Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.
-
公开(公告)号：IT1281028B1
公开(公告)日：1998-02-11
申请号：ITTO950914
申请日：1995-11-13
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , PELLEGRINO PAOLO
Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.
-
公开(公告)号：ITTO950914A1
公开(公告)日：1997-05-13
申请号：ITTO950914
申请日：1995-11-13
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , PELLEGRINO PAOLO
Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.
-
公开(公告)号：IT1268070B1
公开(公告)日：1997-02-20
申请号：ITTO940462
申请日：1994-06-06
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA VALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.028 seconds)
