公开(公告)号：EP0582370A3

公开(公告)日：1994-02-16

申请号：EP93304372.1

申请日：1993-06-04

Applicant: Compaq Computer Corporation

Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主控接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主控接口，兼容接口和缓冲存储器之间的DMA控制器。 DMA控制器也提供在磁盘接口和缓冲存储器之间。 其中一个DMA通道包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环以允许访问缓冲存储器和磁盘接口。 张贴的写入存储器系统作为可选磁盘驱动器连接到磁盘接口。 发布的写入存储器系统包括镜像，奇偶校验和电池支持的半导体存储器，以允许在掉电条件下保留发布的写入数据，而只需要非常小的数据丢失改变。

公开(公告)号：EP0427119A3

公开(公告)日：1993-08-04

申请号：EP90120978.3

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Grieff, Thomas W. ,  Bush, Kenneth L.

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F11/10 ,  G06F11/1008 ,  G06F2003/0692

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

公开(公告)号：EP0486230A1

公开(公告)日：1992-05-20

申请号：EP91310354.5

申请日：1991-11-08

Applicant: Compaq Computer Corporation

Inventor： Lattin, Thomas W., Jr. ,  Grieff, Thomas W. ,  Callison, Ryan A.

IPC: G06F15/16 ,  G06F5/06

CPC classification number: G06F13/4226 ,  G06F13/124

Abstract: A SCSI bus controller (S) has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, (36) the other port of which is connected to a bus master controller (20) linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO (42). The local microprocessor (24) does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.

Abstract translation: SCSI总线控制器（S）具有从SCSI总线到主机总线的单独的数据路径，以及用于与本地微处理器通信的单独的命令路径。 本地微处理器连接到双端口RAM（36），另一个端口连接到与主机系统相连的总线主控制器（20）。 命令和状态通过双端口RAM传递。 数据通过FIFO（42）传递。 本地微处理器（24）不能访问数据路径，而仅控制数据流的方向，序列的启动和序列的完成。

公开(公告)号：EP0427119A2

公开(公告)日：1991-05-15

申请号：EP90120978.3

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Grieff, Thomas W. ,  Bush, Kenneth L.

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0601 ,  G06F11/10 ,  G06F11/1008 ,  G06F2003/0692

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主机接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主机接口，兼容接口和缓冲存储器之间的DMA控制器。 磁盘接口和缓冲存储器之间也提供DMA控制器。 这些DMA通道之一包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环，以允许访问缓冲存储器和磁盘接口。