公开(公告)号：EP0582370A3

公开(公告)日：1994-02-16

申请号：EP93304372.1

申请日：1993-06-04

Applicant: Compaq Computer Corporation

Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主控接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主控接口，兼容接口和缓冲存储器之间的DMA控制器。 DMA控制器也提供在磁盘接口和缓冲存储器之间。 其中一个DMA通道包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环以允许访问缓冲存储器和磁盘接口。 张贴的写入存储器系统作为可选磁盘驱动器连接到磁盘接口。 发布的写入存储器系统包括镜像，奇偶校验和电池支持的半导体存储器，以允许在掉电条件下保留发布的写入数据，而只需要非常小的数据丢失改变。

公开(公告)号：EP0858036A2

公开(公告)日：1998-08-12

申请号：EP98300808.7

申请日：1998-02-04

Applicant: Compaq Computer Corporation

Inventor： Skidmore, Alan E. ,  Schultz, Stephen M. ,  Scholhamer, George J. ,  Thompson, Mark J. ,  Rushton, Tod D. ,  Freeman, Eugene E. ,  Alexander, Dennis J. ,  Callison, Ryan A. ,  Grieff, Thomas W. ,  Sabotta, Michael L. ,  Grant, David L. ,  McCarty, James F. ,  Schneider, Randy D. ,  Galloway, William C.

IPC: G06F13/42 ,  G06F3/06 ,  H04L29/06

CPC classification number: G06F11/201 ,  H04L12/433 ,  H04L67/42

Abstract: A system and/or network (50) for connecting at least one server (52) to at least one storage device (56) via a Fibre Channel (54). Such a system is capable of providing connection redundancy, high speed data rates, multiple operating systems and, hot plugging. Furthermore, the system allows for a large number of devices to be connected to the Fibre Channel. The devices, being servers, storage devices, or other system related appliances can be separated by more than 10 miles and still communicate via the Fibre Channel at high data rates.

Abstract translation: 一种用于经由光纤通道（54）将至少一个服务器（52）连接到至少一个存储设备（56）的系统和/或网络（50）。 这样的系统能够提供连接冗余，高速数据速率，多个操作系统和热插拔。 此外，系统允许大量设备连接到光纤通道。 作为服务器，存储设备或其他系统相关设备的设备可以分开超过10英里，并且仍然通过光纤通道以高数据速率进行通信。

公开(公告)号：EP0582370A2

公开(公告)日：1994-02-09

申请号：EP93304372.1

申请日：1993-06-04

Applicant: Compaq Computer Corporation

Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Abstract translation: 磁盘阵列控制器包括本地微处理器，总线主机接口，兼容接口，缓冲存储器和磁盘接口。 控制器包括微处理器，总线主机接口，兼容接口和缓冲存储器之间的DMA控制器。 磁盘接口和缓冲存储器之间也提供DMA控制器。 这些DMA通道之一包括用于开发与磁盘阵列一起使用的奇偶校验信息的XOR引擎。 各种DMA控制器循环，以允许访问缓冲存储器和磁盘接口。 作为可选择的磁盘驱动器将已写入的存储器系统连接到磁盘接口。 贴出的写入存储器系统包括镜像，奇偶校验和电池供电的半导体存储器，以便在断电条件下保留发布的写入数据，只有非常小的数据丢失变化。

公开(公告)号：EP0858036A3

公开(公告)日：1999-12-22

申请号：EP98300808.7

申请日：1998-02-04

Applicant: Compaq Computer Corporation

Inventor： Skidmore, Alan E. ,  Schultz, Stephen M. ,  Scholhamer, George J. ,  Thompson, Mark J. ,  Rushton, Tod D. ,  Freeman, Eugene E. ,  Alexander, Dennis J. ,  Callison, Ryan A. ,  Grieff, Thomas W. ,  Sabotta, Michael L. ,  Grant, David L. ,  McCarty, James F. ,  Schneider, Randy D. ,  Galloway, William C.

IPC: G06F13/42 ,  G06F3/06 ,  H04L29/06

CPC classification number: G06F11/201 ,  H04L12/433 ,  H04L67/42

Abstract: A system and/or network (50) for connecting at least one server (52) to at least one storage device (56) via a Fibre Channel (54). Such a system is capable of providing connection redundancy, high speed data rates, multiple operating systems and, hot plugging. Furthermore, the system allows for a large number of devices to be connected to the Fibre Channel. The devices, being servers, storage devices, or other system related appliances can be separated by more than 10 miles and still communicate via the Fibre Channel at high data rates.

公开(公告)号：EP0582370B1

公开(公告)日：1998-10-07

申请号：EP93304372.1

申请日：1993-06-04

Applicant: Compaq Computer Corporation

Inventor： Alexander, Dennis J. ,  Callison, Ryan A. ,  Perry, Ralph S.

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0601 ,  G06F11/1012 ,  G06F11/1076 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/74 ,  G11C29/88

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.