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    Negative feedback circuit to control the duty cycle of a logic system clock
    11.
    发明公开
    Negative feedback circuit to control the duty cycle of a logic system clock 失效
    用于控制时钟的占空比为一个逻辑系统的负反馈电路。

    公开(公告)号：EP0398751A2

    公开(公告)日：1990-11-22

    申请号：EP90305428.6

    申请日：1990-05-18

    Applicant: Compaq Computer Corporation

    Inventor： Miller, Joseph P.

    IPC: H03K5/156

    CPC classification number: H03K5/1565

    Abstract: A circuit for controlling the duty cycle of a high frequency logic system clock using negative feedback. A high-level buffer (18) used to drive the system clock bus receives the output of a crystal oscillator (40). The buffer output (50) is sampled by an integrator circuit which produces a voltage level corresponding to the duty cycle of the clock, and this voltage level is compared to a reference voltage using an operational amplifier (60). The op-amp output (70) is applied to the buffer input (75) as negative feedback to alter the bias level at the buffer input (75) in a way as to vary the point in the rising and falling transitions of the crystal oscillator (40) where the threshold of the buffer (48) is crossed. A circuit (52,54) monitors the clock signal output of a high-level buffer (48), and determines whether the duty cycle of the crystal oscillator (40) which drives the output buffer (48) should be increased or decreased. A corresponding DC bias to the input of the output buffer (48) causes the crystal oscillator (40) output to reach threshold levels of the output buffer (48) at different times during each clock pulse, thus adjusting the duty cycle of the buffer output (50). An RC integrator (52,54) is used to monitor the buffer output, and the output of this integrator is compared with a reference voltage in an operational amplifier (60). The output of the operational amplifier (60) biases the input (75) to the output buffer (48) to a level corresponding to a need to increase or decrease the duty cycle of the buffer output clock signal.

    Abstract translation: 一种用于控制使用负反馈的高频逻辑系统时钟的占空比电路。 用于驱动系统时钟总线的高级别缓冲器（18）接收一个晶体振荡器（40）的输出。 缓冲器输出（50）是通过在积分器电路，其产生的电压电平对应于该时钟的占空比进行采样，并且该电压电平进行比较，在使用运算放大器（60）的基准电压。 所述运算放大器的输出（70）被施加到所述缓冲器输入（75）作为负反馈，以改变在一个方式的缓冲器输入（75）的偏置电平，以在晶体振荡器的转换的上升和下降变化点 （40），其中所述缓冲液（48）的阈值交叉。 一种电路（52,54）监视一个高层次的缓冲器（48）的输出的时钟信号，并且无论是晶体振荡器（40），其驱动所述输出缓冲器（48）的占空比应该被增加或减少确定性地雷。 相应的DC偏压到输出缓冲器（48）的输入，使晶体振荡器（40）输出的每个时钟脉冲期间达到在不同的时间输出缓冲器（48）的阈值水平，从而调节所述缓冲器输出的占空比 （50）。 一个RC积分器（52,54）用于监视缓冲器输出，并且该积分器的输出与在运算放大器（60）中的参考电压进行比较。 运算放大器（60）的输出偏压输入（75）连接到输出缓冲器（48）的电平对应于需要增加或减小输出缓冲器时钟信号的占空比。

    Bus ring-back and voltage over-shoot reduction techniques in a hot-plugging computer system
    13.
    发明公开
    Bus ring-back and voltage over-shoot reduction techniques in a hot-plugging computer system 审中-公开
    技术在张力下的计算机系统中减少Busrückspannung和电压过冲在可插入的

    公开(公告)号：EP0898231A3

    公开(公告)日：2000-02-02

    申请号：EP98306457.7

    申请日：1998-08-13

    Applicant: Compaq Computer Corporation

    Inventor： Tavallaei, Siamak ,  Miller, Joseph P.

    IPC: G06F13/40

    CPC classification number: G06F13/4081

    Abstract: A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot (408) of a computer system hot-pluggable, wherein a logic gate (406) controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card (410) whereas the other node is coupled to a bus (404) to which the expansion slot is connected. The apparatus (406) operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card (410) from the bus (404) when the system is running or during the powering up of the card.

    Computer system fault diagnosis
    14.
    发明公开
    Computer system fault diagnosis 失效
    Fehlerdiagnosefürein Rechnersystem

    公开(公告)号：EP0840226A1

    公开(公告)日：1998-05-06

    申请号：EP97308217.5

    申请日：1997-10-16

    Applicant: Compaq Computer Corporation

    Inventor： Culley, Paul R. ,  Miller, Joseph P. ,  Hull, Daniel S. ,  Tavallaei, Siamak

    IPC: G06F11/22

    CPC classification number: G06F11/0745 ,  G06F11/0748 ,  G06F11/079

    Abstract: Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

    Abstract translation: 具有电路的计算机系统中的故障由连接的故障检测器来管理，以检测各个电路的故障状态。 故障管理器将故障状态与相应的电路相关联。 故障管理器包括连接到系统管理器以识别哪些电路在计算机系统中导致故障的操作。 与相应电路相关联的故障检测器被配置为检测各个电路的故障运行和产生故障状态信息。 连接中央管理器来累积故障检测器的故障状态信息。 其中一个电路包括总线，故障状态包括总线错误状况。 总线连接到多个设备，故障管理器识别多个设备中的哪一个引起总线错误状况。 其中一个电路包括多个模块，故障管理器识别多个模块的故障状态。 模块包括状态机。 其中一个电路包括内部时钟，电路的故障状态包括内部时钟不能正常工作。 其中一个电路包括温度传感器，并且电路的故障状态包括由温度传感器检测的高温条件。

    Negative feedback circuit to control the duty cycle of a logic system clock
    16.
    发明公开
    Negative feedback circuit to control the duty cycle of a logic system clock 失效
    负反馈电路控制逻辑系统时钟的占空比

    公开(公告)号：EP0398751A3

    公开(公告)日：1991-03-20

    申请号：EP90305428.6

    申请日：1990-05-18

    Applicant: Compaq Computer Corporation

    Inventor： Miller, Joseph P.

    IPC: H03K5/156

    CPC classification number: H03K5/1565

    Abstract: A circuit for controlling the duty cycle of a high frequency logic system clock using negative feedback. A high-level buffer (18) used to drive the system clock bus receives the output of a crystal oscillator (40). The buffer output (50) is sampled by an integrator circuit which produces a voltage level corresponding to the duty cycle of the clock, and this voltage level is compared to a reference voltage using an operational amplifier (60). The op-amp output (70) is applied to the buffer input (75) as negative feedback to alter the bias level at the buffer input (75) in a way as to vary the point in the rising and falling transitions of the crystal oscillator (40) where the threshold of the buffer (48) is crossed. A circuit (52,54) monitors the clock signal output of a high-level buffer (48), and determines whether the duty cycle of the crystal oscillator (40) which drives the output buffer (48) should be increased or decreased. A corresponding DC bias to the input of the output buffer (48) causes the crystal oscillator (40) output to reach threshold levels of the output buffer (48) at different times during each clock pulse, thus adjusting the duty cycle of the buffer output (50). An RC integrator (52,54) is used to monitor the buffer output, and the output of this integrator is compared with a reference voltage in an operational amplifier (60). The output of the operational amplifier (60) biases the input (75) to the output buffer (48) to a level corresponding to a need to increase or decrease the duty cycle of the buffer output clock signal.

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