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    Bus ring-back and voltage over-shoot reduction techniques in a hot-plugging computer system
    1.
    发明公开
    Bus ring-back and voltage over-shoot reduction techniques in a hot-plugging computer system 审中-公开
    技术在张力下的计算机系统中减少Busrückspannung和电压过冲在可插入的

    公开(公告)号：EP0898231A2

    公开(公告)日：1999-02-24

    申请号：EP98306457.7

    申请日：1998-08-13

    Applicant: Compaq Computer Corporation

    Inventor： Tavallaei, Siamak ,  Miller, Joseph P.

    IPC: G06F13/40

    CPC classification number: G06F13/4081

    Abstract: A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot (408) of a computer system hot-pluggable, wherein a logic gate (406) controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card (410) whereas the other node is coupled to a bus (404) to which the expansion slot is connected. The apparatus (406) operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card (410) from the bus (404) when the system is running or during the powering up of the card.

    Abstract translation: 总线回铃和电压过冲降低装置与能力用于再现可热插拔的计算机系统的扩展槽（408）的，worin一个逻辑门（406）控制开关元件，以便做当元件被接通时， 该元件的输入和输出（I / O）节点处于低欧姆导电关系。 一个I / O节点中的，而另一节点耦合到一个总线（404）连接到扩展槽连接扩充哪个卡（410）被耦合到。 的装置（406）操作为worin输出节点电压如下检查做的输出电压，直到夹断所述输入电压节点的电平移位器保持基本稳定之后。 当系统正在运行或卡的加电过程中的装置，从而隔离所述总线（404）的扩展卡（410）。

    Quadruple word, multiplexed, paged mode and cache memory
    2.
    发明公开
    Quadruple word, multiplexed, paged mode and cache memory 失效
    Vierfachwort-，Multiplex-Seitenmodusspeicher und Cache-Speicher。

    公开(公告)号：EP0398191A2

    公开(公告)日：1990-11-22

    申请号：EP90108942.5

    申请日：1990-05-11

    Applicant: Compaq Computer Corporation

    Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

    IPC: G06F12/08

    CPC classification number: G06F12/0886

    Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

    Abstract translation: 64位宽的存储器通过32位数据总线复用，以提供数据到由82385缓存控制器控制的64位行大小的高速缓冲存储器。 在整个传输过程中，保存所有64位存储器的存储器地址，从而发生零等待状态第二次32位传输。 逻辑开发所需的下一个地址和就绪脉冲，并从缓存控制器中阻止这些信号。 逻辑还处理主和高速缓冲存储器的位2地址。 主存储器以分页模式运行，以进一步提高系统性能。

    Fault isolation
    3.
    发明公开
    Fault isolation 失效
    Fehlereingrenzung

    公开(公告)号：EP0820012A2

    公开(公告)日：1998-01-21

    申请号：EP97303790.6

    申请日：1997-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Goodrum, Alan L. ,  Autor, Jeffrey S. ,  Culley, Paul R. ,  Miller, Joseph P. ,  Tavallaei, Siamak ,  Basile, Barry S. ,  Richard, Elizabeth A. ,  Rose, Eric E.

    IPC: G06F11/273

    CPC classification number: G06F11/2005 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/2007 ,  G06F11/2012 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/349

    Abstract: A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

    Abstract translation: 在具有设备的计算机系统中导致故障状态的设备通过检测与设备相关联的故障状况并识别引起故障状态的设备而被隔离。 这些设备耦合到总线。 故障状况包括总线挂起状况。 当检测到总线挂起状态时，设备被关闭。 然后将设备重新打开以测试设备。 每个设备都通过写入和读取其配置空间进行测试。 存储与故障条件相关的总线上的信息。 所存储的信息在故障状态发生之后被检索，存储的信息包括地址，数据和总线控制信息。

    Computer system host switching
    4.
    发明公开
    Computer system host switching 失效
    计算机系统主机切换

    公开(公告)号：EP0817055A2

    公开(公告)日：1998-01-07

    申请号：EP97303800.3

    申请日：1997-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Goodrum, Alan L. ,  Sides, Chi Kim ,  Miller, Joseph P. ,  Cox, Tod B. ,  Cook, M. Damian ,  Sanders, Michael C.

    IPC: G06F11/20

    CPC classification number: G06F11/2025 ,  G06F11/0757 ,  G06F11/142 ,  G06F11/2002 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/22 ,  G06F13/4022

    Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

    Abstract translation: 控制从容错系统中的第一个服务器切换到第二个服务器。 第一和第二服务器与用于与扩展总线通信的扩展盒中的扩展总线连接。 向第二服务器提供指示以指示第一服务器的活动状态。 如果指示表明第一台服务器处于非活动状态，则第一台服务器和扩展盒之间的通信将被禁用。 如果指示表明第一台服务器处于活动状态，则第二台服务器和扩展总线之间的通信将被禁用。 如果该指示指示第一服务器不活动，则启用第二服务器之间的通信。 该指示包括周期性发送给第二服务器的心跳消息。 扩展总线包括一个PCI总线。

    Data synchronization between two devices
    6.
    发明公开
    Data synchronization between two devices 失效
    Datensynchronisierung zwischen zweiGeräten

    公开(公告)号：EP0811928A2

    公开(公告)日：1997-12-10

    申请号：EP97303793.0

    申请日：1997-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Goodrum, Alan L. ,  Ramsey, Jens K. ,  Culley, Paul R. ,  Miller, Joseph P.

    IPC: G06F13/40

    CPC classification number: G06F13/405

    Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer. The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

    Abstract translation: 在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。 第一设备产生第一时钟，第二设备产生第二时钟。 第一时钟被提供给第二设备，并且第二时钟提供给第一设备。 由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。 第一设备中的接收逻辑包括先进先出缓冲器。 接收的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。 第一和第二时钟具有相同的频率。

    Data synchronization between two devices
    9.
    发明公开
    Data synchronization between two devices 失效
    两个设备之间的数据同步

    公开(公告)号：EP0811928A3

    公开(公告)日：1999-02-10

    申请号：EP97303793.0

    申请日：1997-06-04

    Applicant: Compaq Computer Corporation

    Inventor： Goodrum, Alan L. ,  Ramsey, Jens K. ,  Culley, Paul R. ,  Miller, Joseph P.

    IPC: G06F13/40

    CPC classification number: G06F13/405

    Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer. The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

    Quadruple word, multiplexed, paged mode and cache memory
    10.
    发明公开
    Quadruple word, multiplexed, paged mode and cache memory 失效
    四字，复用，分页模式和高速缓冲存储器

    公开(公告)号：EP0398191A3

    公开(公告)日：1991-11-27

    申请号：EP90108942.5

    申请日：1990-05-11

    Applicant: Compaq Computer Corporation

    Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

    IPC: G06F12/08

    CPC classification number: G06F12/0886

    Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

    Abstract translation: 64位宽的存储器通过32位数据总线进行多路复用，以将数据提供给由82385高速缓存控制器控制的64位线路大小的高速缓冲存储器。 所有64位存储器的存储器地址在整个传输过程中保持不变，以便发生零等待状态秒32位传输。 逻辑开发必要的下一个地址和就绪脉冲并阻止来自缓存控制器的这些信号。 逻辑还处理主存储器和高速缓存存储器的第2位地址。 主内存以分页模式运行，以进一步提高系统性能。

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