公开(公告)号：EP0811932B1

公开(公告)日：2003-04-09

申请号：EP97303798.9

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Culley, Paul R. ,  Chow, Raymond Y.L. ,  Basile, Barry S. ,  Waldorf, Richard O. ,  Cook, Pamela M. ,  Mar, Clarence Y.

IPC: G06F13/40

CPC classification number: G06F13/4081

公开(公告)号：EP0811938A3

公开(公告)日：1999-08-04

申请号：EP97303807.8

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Whiteman, William F. ,  Goodrum, Alan L. ,  Cox, Tod B. ,  Basile, Barry S.

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/404

Abstract: A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I 2 O processor, and the second bus device may be an I 2 O subordinate bus device.

公开(公告)号：EP0811933A3

公开(公告)日：1999-02-24

申请号：EP97303803.7

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Maclaren, John M. ,  Culley, Paul R.

IPC: G06F13/40

CPC classification number: G06F13/4059

Abstract: A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

公开(公告)号：EP0445463A1

公开(公告)日：1991-09-11

申请号：EP90311701.8

申请日：1990-10-25

Applicant: Compaq Computer Corporation

Inventor： Mayer, Dale J. ,  Culley, Paul R. ,  Goodrum, Alan L.

IPC: G06F13/42

CPC classification number: G06F13/4243

Abstract: A memory controller (62) provides a stretch signal to a bus controller (48) which develops the synchronizing signal (BGLK) used on a synchronized bus (46), alleviating the need to insert a full wait state during memory read operations. The memory (58) is located off a second bus (44) which is tightly coupled to the processor (20), but devices operating according to the protocol of the synchronized bus can access the memory. The memory controller (62) controls the buffers and address multiplexing between the second bus and the memory devices, while the bus controller (48) controls the buffering and latching between the first and second buses. The memory controller also develops the row and column address strobes used by the memory devices.

Abstract translation: 存储器控制器（62）向总线控制器（48）提供拉伸信号，该总线控制器产生在同步总线（46）上使用的同步信号（BGLK），从而减轻了在存储器读取操作期间插入完整等待状态的需要。 存储器（58）位于与处理器（20）紧密耦合的第二总线（44）之外，但是根据同步总线的协议操作的设备可以访问存储器。 存储器控制器（62）控制缓冲器并且在第二总线和存储器件之间寻址多路复用，而总线控制器（48）控制第一和第二总线之间的缓冲和锁存。 存储器控制器还开发存储器件使用的行和列地址选通。

公开(公告)号：EP0817055B1

公开(公告)日：2003-05-02

申请号：EP97303800.3

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Sides, Chi Kim ,  Miller, Joseph P. ,  Cox, Tod B. ,  Cook, M. Damian ,  Sanders, Michael C.

IPC: G06F11/20

CPC classification number: G06F11/2025 ,  G06F11/0757 ,  G06F11/142 ,  G06F11/2002 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/22 ,  G06F13/4022

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

公开(公告)号：EP0845743A3

公开(公告)日：1999-08-18

申请号：EP97309417.0

申请日：1997-11-21

Applicant: Compaq Computer Corporation

Inventor： Cox, B. Tod ,  Goodrum, Alan L.

IPC: G06F13/12

CPC classification number: G06F13/24

Abstract: A method and apparatus for enabling a computer user to implement intelligent input/output processing involves a connector adapted to receive interrupt request signals from input/output devices in a plurality of slots contained on an input/output bus. When an intelligent input/output card is inserted into the connector, the card can process certain of the interrupt requests from devices contained in slots connected to the input/output bus. This augments the processing of input/output device interrupt requests without burdening the host processor. Thus, a computer system arranged in a peer architecture may be subsequently enhanced with a intelligent input/output card, without burdening all purchasers with the cost of expensive hardware to enable the subsequent upgrade.

公开(公告)号：EP0845743A2

公开(公告)日：1998-06-03

申请号：EP97309417.0

申请日：1997-11-21

Applicant: Compaq Computer Corporation

Inventor： Cox, B. Tod ,  Goodrum, Alan L.

IPC: G06F13/12

CPC classification number: G06F13/24

Abstract: A method and apparatus for enabling a computer user to implement intelligent input/output processing involves a connector adapted to receive interrupt request signals from input/output devices in a plurality of slots contained on an input/output bus. When an intelligent input/output card is inserted into the connector, the card can process certain of the interrupt requests from devices contained in slots connected to the input/output bus. This augments the processing of input/output device interrupt requests without burdening the host processor. Thus, a computer system arranged in a peer architecture may be subsequently enhanced with a intelligent input/output card, without burdening all purchasers with the cost of expensive hardware to enable the subsequent upgrade.

Abstract translation: 一种用于使计算机用户来实现智能输入/输出处理方法和装置，涉及连接器angepasst在包含在到输入/输出总线的时隙的多元性以接收来自输入/输出设备的中断请求信号。 当一个智能输入/输出卡被插入到该连接器，该卡可以处理某些从包含在连接到输入/输出总线插槽中的设备的中断请求。 这增强了输入/输出装置的中断请求的处理而无需负担主机处理器。 因此，在对等体架构布置的计算机系统随后可以与智能输入/输出卡增强，而不负担昂贵的硬件成本所有购买，以使随后的升级。

公开(公告)号：EP0817055A3

公开(公告)日：1998-04-22

申请号：EP97303800.3

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Sides, Chi Kim ,  Miller, Joseph P. ,  Cox, Tod B. ,  Cook, M. Damian ,  Sanders, Michael C.

IPC: G06F11/20

CPC classification number: G06F11/2025 ,  G06F11/0757 ,  G06F11/142 ,  G06F11/2002 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/22 ,  G06F13/4022

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

公开(公告)号：EP0821310A2

公开(公告)日：1998-01-28

申请号：EP97303795.5

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  MacLaren, John M. ,  Pettey, Christopher J. ,  Culley, Paul R.

IPC: G06F13/364 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F13/4054

Abstract: A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

Abstract translation: 计算机系统包括在第一数据总线上的数据存储装置，在第二数据总线上发起延迟请求的请求装置，以及将延迟的请求传送到第一数据总线的桥接装置，并且在请求装置重新获得控制之后 的第二数据总线开始向数据存储设备提供所请求的数据到桥设备时向请求设备提供数据。

公开(公告)号：EP0817088A2

公开(公告)日：1998-01-07

申请号：EP97303802.9

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L.

IPC: G06F13/40

CPC classification number: G06F13/4045

Abstract: A computer system includes a data storage device on a first data bus, a requesting device that initiates a request for data on a second data bus, and a bridge device that delivers the request to the first data bus and receives the requested data from the data storage device. The bridge device includes a data storage buffer that temporarily stores the requested data, and a buffer management element that flushes the data from the buffer when the requesting device initiates a new request for data other than the data stored in the buffer.

Abstract translation: 计算机系统包括在第一数据总线上的数据存储设备，在第二数据总线上启动数据请求的请求设备，以及将请求传送到第一数据总线并从数据中接收所请求的数据的桥接设备 储存设备。 桥接器件包括临时存储所请求的数据的数据存储缓冲器，以及缓冲器管理元件，当请求器件发起对存储在缓冲器中的数据以外的数据的新请求时，缓冲器管理元件从缓冲器中刷新数据。