公开(公告)号：EP1722408A1

公开(公告)日：2006-11-15

申请号：EP06075882.8

申请日：2006-04-13

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Mars, Jeffrey A. ,  Jay, Ian D. ,  Wyant, Johnna L. ,  Ihms, David W. ,  Isenberg, John K. ,  Worl, Roger E.

IPC: H01L21/56 ,  H01L21/60 ,  G01L9/00

CPC classification number: H01L24/81 ,  G01L9/0073 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/1132 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method of flip-chip mounting a circuit device (12) to a substrate (10) in a manner that avoids damage and impairment of a fragile or otherwise sensitive element (30) on the device (12) facing the substrate (10), and a circuit assembly (60) produced thereby. The assembly (60) includes a substrate (10) having at least two sets of bonding sites (16) spaced apart from each other to define an intermediate surface region (18) therebetween. The device (12) is attached to the bonding sites (16) with solder connections (56,58), with the solder connections (56,58) being present on a surface of the device (12) that faces the substrate (10) and on which the element (30) is present so that the element (30) overlies the intermediate surface region (18) of the substrate (10). An underfill material (62) is present between the device (12) and the substrate (10) and encapsulates the solder connections (56,58). The underfill material (62) is separated from the intermediate surface region (18) of the substrate (10) so that the underfill material (62) does not contact the element (30).

Abstract translation: 一种以避免在面向衬底（10）的器件（12）上的脆弱或其他敏感元件（30）的损坏和损坏的方式将电路器件（12）倒装安装到衬底（10）的方法， 和由此产生的电路组件（60）。 组件（60）包括具有彼此间隔开的至少两组结合位置（16）的衬底（10），以在它们之间限定中间表面区域（18）。 设备（12）通过焊接连接（56,58）附接到焊接点（16），焊料连接（56,58）存在于与衬底（10）相对的器件（12）的表面上， 并且其上存在元件（30），使得元件（30）覆盖在基板（10）的中间表面区域（18）上。 在装置（12）和衬底（10）之间存在底部填充材料（62）并封装焊料连接（56,58）。 底部填充材料（62）与衬底（10）的中间表面区域（18）分离，使得底部填充材料（62）不与元件（30）接触。

公开(公告)号：EP1333504A2

公开(公告)日：2003-08-06

申请号：EP03075163.0

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Lee, Han-Sheng ,  Lambert, David K. ,  Vas, Timothy A.

IPC: H01L35/02 ,  H01L35/08

CPC classification number: G01J5/14 ,  G01J5/12

Abstract: An integrated sensor (10) comprising a thermopile transducer (12) and signal processing circuitry (4) that are combined on a single semiconductor substrate (20), such that the transducer output signal is sampled in close vicinity by the processing circuitry (14). The sensor (10) comprises a frame (18) formed of a semiconductor material that is not heavily doped, and with which a diaphragm (16) is supported. The diaphragm (16) has a first surface for receiving thermal (e.g., infrared) radiation, and comprises multiple layers that include a sensing layer containing at least a pair of interlaced thermopiles (22). Each thermopile (22) comprises a sequence of thermocouples (24), each thermocouple (24) comprising dissimilar electrically-resistive materials that define hot junctions (26) located on the diaphragm (16) and cold junctions (28) located on the frame (18). The signal processing circuitry (14) is located on the frame (18) and electrically interconnected with the thermopiles (22). The thermopiles (22) are interlaced so that the output of one of the thermopiles (22) increases with increasing temperature difference between the hot and cold junctions (26,28) thereof, while the output of the second thermopile (22) decreases with increasing temperature difference between its hot and cold junctions (26,28).

Abstract translation: 包括组合在单个半导体衬底（20）上的热电堆换能器（12）和信号处理电路（4）的集成传感器（10），使得所述换能器输出信号在所述处理电路（14）附近被采样， 。 传感器（10）包括由不重掺杂的半导体材料形成的框架（18），并且支撑有隔膜（16）。 隔膜（16）具有用于接收热（例如，红外线）辐射的第一表面，并且包括包含至少一对隔行热电堆（22）的感测层的多个层。 每个热电堆（22）包括一系列热电偶（24），每个热电偶（24）包括不同的电阻材料，其限定位于隔膜（16）上的热接点（26）和位于框架上的冷接点（28） 18）。 信号处理电路（14）位于框架（18）上并与热电堆（22）电互连。 热电堆（22）交错，使得其中一个热电堆（22）的输出随着热连接点（26,28）之间温差的增加而增加，而第二热电堆（22）的输出随着增加 其热连接点之间的温差（26,28）。