公开(公告)号：EP1333504B1

公开(公告)日：2013-04-24

申请号：EP03075163.0

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Lee, Han-Sheng ,  Lambert, David K. ,  Vas, Timothy A.

IPC: G01J5/12 ,  G01J5/14

CPC classification number: G01J5/14 ,  G01J5/12

公开(公告)号：EP1345014A1

公开(公告)日：2003-09-17

申请号：EP03075191.1

申请日：2003-01-21

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Manlove, Gregory J.

IPC: G01F15/02 ,  G05F5/00

CPC classification number: G01F1/696 ,  G01F15/046 ,  Y10S323/907

Abstract: A non-linear temperature compensation circuit (10) is provided for generating at least dual-slope characteristics responsive to changes in operating temperature of the compensation circuit. The compensation circuit includes a temperature dependent current generator circuit (11) for generating at least one output (I4) substantially proportional to changes in the temperature of the circuit, a current-based dual-slope drift generator (12) for generating a current proportional to absolute temperature, and a summing means (14) for summing both current outputs and generating a compensation drift voltage. The temperature dependent current generator includes a sub-circuit having a first current generator that generates a current (I2) that is relatively independent of temperature, and a second current generator that generates a second current (I3) that decreases with increases in temperature. The two currents are compared and a non-zero output current (I4) is generated if the second current (I3) exceeds the first current (I2), which output current (I4) decreases with increases in temperature.

Abstract translation: 提供了非线性温度补偿电路（10），用于响应于补偿电路的工作温度的变化产生至少双斜率特性。 补偿电路包括温度依赖性电流发生器电路（11），用于产生基本上与电路温度变化成比例的至少一个输出（I4），用于产生电流成比例的电流双斜率漂移发生器（12） 和绝对温度的求和装置（14），用于对电流输出进行求和并产生补偿漂移电压。 温度相关电流发生器包括具有产生与温度相对独立的电流（I2）的第一电流发生器的子电路和产生随着温度升高而降低的第二电流（I3）的第二电流发生器。 如果第二电流（I3）超过第一电流（I2），则输出电流（I4）随着温度的升高而减小，则比较两个电流并产生非零输出电流（I4）。

公开(公告)号：EP1333502A3

公开(公告)日：2008-11-19

申请号：EP03075165.5

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Logsdon, James H. ,  Chavan, Abhijeet V. ,  Borzabadi, Hamid R.

IPC: H01L31/0203

CPC classification number: H01L25/167 ,  H01L23/10 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An optical sensor package (10) capable of being surface mounted, and in a form that enables multiple packages (10) to be fabricated simultaneously and then array tested in a wafer stack prior to singulation. The package (10) comprises a chip carrier (12), a device chip (16) electrically and mechanically connected to a first surface of the chip carrier (12) with solder connections (32), and a capping chip (14) secured to the chip carrier (12) to hermetically enclose the device chip (16). The device chip (16) has an optical sensing element on a surface thereof, while the capping chip (14) has means (14,22,24) for enabling radiation to pass therethrough to the device chip (16). The chip carrier (12) includes conductive vias (28) that are electrically connected to the solder connections (32) of the device chip (16) and extend through the chip carrier (12) to bond pads (34) on a second surface of the chip carrier (12), enabling the package (10) to be surface mounted with solder connections (40) to a suitable substrate (36).

公开(公告)号：EP1333503A2

公开(公告)日：2003-08-06

申请号：EP03075166.3

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Christenson, John C. ,  Speck, Robert K.

IPC: H01L35/00 ,  H01L27/16

CPC classification number: B81B3/0072 ,  B81B2201/0278 ,  B81B2203/0127 ,  G01J5/02 ,  G01J5/024 ,  G01J5/12 ,  H01L27/16 ,  H01L2224/48463

Abstract: A process using integrated sensor technology in which a micromachined sensing element (12) and signal processing circuit (14) are combined on a single semiconductor substrate (20) to form, for example, an infrared sensor (10). The process is based on modifying a CMOS process to produce an improved layered micromachined member, such as a diaphragm (16), after the circuit fabrication process is completed. The process generally entails forming a circuit device (14) on a substrate (20) by processing steps that include forming multiple dielectric layers (34,36,38,44,46) and at least one conductive layer (40,50) on the substrate (20). The dielectric layers (34,36,38,44,46) comprise an oxide layer (34) on a surface of the substrate (20) and at least two dielectric layers (36,46) that are in tension, with the conductive layer (40,50) being located between the two dielectric layers (36,46). The surface of the substrate (20) is then dry etched to form a cavity (32) and delineate the diaphragm (16) and a frame (18) surrounding the diaphragm (16). The dry etching step terminates at the oxide layer (34), such that the diaphragm (16) comprises the dielectric layers (34,36,38,44,46) and conductive layer (40,50). A special absorber (52) is preferably fabricated on the diaphragm (16) to promote efficient absorption of incoming infrared radiation.

Abstract translation: 一种使用集成传感器技术的方法，其中微机械感测元件（12）和信号处理电路（14）组合在单个半导体衬底（20）上以形成例如红外传感器（10）。 该方法基于在电路制造过程完成之后修改CMOS工艺以产生改进的分层微加工构件，例如隔膜（16）。 该方法通常需要通过处理步骤在衬底（20）上形成电路器件（14），该步骤包括在其上形成多个电介质层（34,36,38,44,46）和至少一个导电层（40,50） 衬底（20）。 电介质层（34,36,38,44,46）在衬底（20）的表面上包括氧化物层（34）和处于张力的至少两个电介质层（36,46），导电层 （40,50）位于两个电介质层（36,46）之间。 然后干燥蚀刻衬底（20）的表面以形成空腔（32）并描绘隔膜（16）和围绕隔膜（16）的框架（18）。 干蚀刻步骤终止在氧化物层（34）处，使得隔膜（16）包括电介质层（34,36,38,44,46）和导电层（40,50）。 优选地，在隔膜（16）上制造特殊吸收器（52）以促进进入的红外辐射的有效吸收。

公开(公告)号：EP1333503B1

公开(公告)日：2011-07-06

申请号：EP03075166.3

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Christenson, John C. ,  Speck, Robert K.

IPC: H01L27/16 ,  H01L35/00 ,  B81B3/00 ,  G01J5/12 ,  G01J5/02

CPC classification number: B81B3/0072 ,  B81B2201/0278 ,  B81B2203/0127 ,  G01J5/02 ,  G01J5/024 ,  G01J5/12 ,  H01L27/16 ,  H01L2224/48463

公开(公告)号：EP1333504A3

公开(公告)日：2007-01-31

申请号：EP03075163.0

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Lee, Han-Sheng ,  Lambert, David K. ,  Vas, Timothy A.

IPC: H01L35/02 ,  H01L35/08

CPC classification number: G01J5/14 ,  G01J5/12

Abstract: An integrated sensor (10) comprising a thermopile transducer (12) and signal processing circuitry (4) that are combined on a single semiconductor substrate (20), such that the transducer output signal is sampled in close vicinity by the processing circuitry (14). The sensor (10) comprises a frame (18) formed of a semiconductor material that is not heavily doped, and with which a diaphragm (16) is supported. The diaphragm (16) has a first surface for receiving thermal (e.g., infrared) radiation, and comprises multiple layers that include a sensing layer containing at least a pair of interlaced thermopiles (22). Each thermopile (22) comprises a sequence of thermocouples (24), each thermocouple (24) comprising dissimilar electrically-resistive materials that define hot junctions (26) located on the diaphragm (16) and cold junctions (28) located on the frame (18). The signal processing circuitry (14) is located on the frame (18) and electrically interconnected with the thermopiles (22). The thermopiles (22) are interlaced so that the output of one of the thermopiles (22) increases with increasing temperature difference between the hot and cold junctions (26,28) thereof, while the output of the second thermopile (22) decreases with increasing temperature difference between its hot and cold junctions (26,28).

公开(公告)号：EP1333503A3

公开(公告)日：2009-11-18

申请号：EP03075166.3

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Chilcott, Dan W. ,  Christenson, John C. ,  Speck, Robert K.

IPC: H01L35/00 ,  H01L27/16

CPC classification number: B81B3/0072 ,  B81B2201/0278 ,  B81B2203/0127 ,  G01J5/02 ,  G01J5/024 ,  G01J5/12 ,  H01L27/16 ,  H01L2224/48463

Abstract: A process using integrated sensor technology in which a micromachined sensing element (12) and signal processing circuit (14) are combined on a single semiconductor substrate (20) to form, for example, an infrared sensor (10). The process is based on modifying a CMOS process to produce an improved layered micromachined member, such as a diaphragm (16), after the circuit fabrication process is completed. The process generally entails forming a circuit device (14) on a substrate (20) by processing steps that include forming multiple dielectric layers (34,36,38,44,46) and at least one conductive layer (40,50) on the substrate (20). The dielectric layers (34,36,38,44,46) comprise an oxide layer (34) on a surface of the substrate (20) and at least two dielectric layers (36,46) that are in tension, with the conductive layer (40,50) being located between the two dielectric layers (36,46). The surface of the substrate (20) is then dry etched to form a cavity (32) and delineate the diaphragm (16) and a frame (18) surrounding the diaphragm (16). The dry etching step terminates at the oxide layer (34), such that the diaphragm (16) comprises the dielectric layers (34,36,38,44,46) and conductive layer (40,50). A special absorber (52) is preferably fabricated on the diaphragm (16) to promote efficient absorption of incoming infrared radiation.

公开(公告)号：EP1672342A1

公开(公告)日：2006-06-21

申请号：EP05077730.9

申请日：2005-11-28

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Slaughter, Deron K. ,  Donahue, Michael P.

IPC: G01J5/12

CPC classification number: G01J5/12

Abstract: A method and apparatus (70) for evaluating the functionality and sensitivity of an infrared sensor (10) to infrared radiation. The method and apparatus (70) are adapted for testing an infrared sensor (10) having a diaphragm (16) containing a heating element (58) and a transducer (12) that generates an output responsive to temperature. The method entails placing the infrared sensor (10) in a controlled environment (72), and then exposing the diaphragm (16) of the sensor (10) to different levels of thermal radiation so as to obtain outputs of the transducer (12) at different output levels. In the absence of exposure of the diaphragm (16) to thermal radiation, flowing current through the heating element (58) at different input levels so that the output of the transducer (12) returns to the different output levels obtained using thermal radiation, the input difference between the input levels can be computed and used to assess the functionality and the sensitivity of the sensor (10).

Abstract translation: 一种用于评估红外传感器（10）对红外辐射的功能和灵敏度的方法和装置（70）。 所述方法和装置（70）适于测试具有包含加热元件（58）的隔膜（16）的红外传感器（10）和产生响应于温度的输出的换能器（12）。 该方法需要将红外传感器（10）放置在受控环境（72）中，然后将传感器（10）的隔膜（16）暴露于不同程度的热辐射，以便获得传感器（12）的输出 不同的输出水平。 在没有将隔膜（16）暴露于热辐射的情况下，流过不同输入电平的加热元件（58）的电流，使得换能器（12）的输出返回到使用热辐射获得的不同的输出电平， 可以计算输入电平之间的输入差异，并用于评估传感器（10）的功能和灵敏度。

公开(公告)号：EP1333502A2

公开(公告)日：2003-08-06

申请号：EP03075165.5

申请日：2003-01-17

Applicant: Delphi Technologies, Inc.

Inventor： Logsdon, James H. ,  Chavan, Abhijeet V. ,  Borzabadi, Hamid R.

IPC: H01L31/0203

CPC classification number: H01L25/167 ,  H01L23/10 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An optical sensor package (10) capable of being surface mounted, and in a form that enables multiple packages (10) to be fabricated simultaneously and then array tested in a wafer stack prior to singulation. The package (10) comprises a chip carrier (12), a device chip (16) electrically and mechanically connected to a first surface of the chip carrier (12) with solder connections (32), and a capping chip (14) secured to the chip carrier (12) to hermetically enclose the device chip (16). The device chip (16) has an optical sensing element on a surface thereof, while the capping chip (14) has means (14,22,24) for enabling radiation to pass therethrough to the device chip (16). The chip carrier (12) includes conductive vias (28) that are electrically connected to the solder connections (32) of the device chip (16) and extend through the chip carrier (12) to bond pads (34) on a second surface of the chip carrier (12), enabling the package (10) to be surface mounted with solder connections (40) to a suitable substrate (36).

Abstract translation: 一种能够被表面安装的光学传感器封装（10），并且以能够在分割之前同时制造多个封装（10）然后在晶片堆叠中进行阵列测试的形式。 封装（10）包括芯片载体（12），利用焊料连接（32）电连接和机械地连接到芯片载体（12）的第一表面的器件芯片（16），和封盖芯片（14）固定到 所述芯片载体（12）气密地包围所述装置芯片（16）。 器件芯片（16）在其表面上具有光学感测元件，而封盖芯片（14）具有用于使辐射能够通过其中的器件芯片（16）的装置（14,22,24）。 芯片载体（12）包括电连接到器件芯片（16）的焊料连接（32）并延伸穿过芯片载体（12）的导电通孔（28），以在第二表面上的接合焊盘 所述芯片载体（12）使所述封装（10）能够被表面安装有焊接连接（40）到合适的衬底（36）。

公开(公告)号：EP1672342B1

公开(公告)日：2008-10-29

申请号：EP05077730.9

申请日：2005-11-28

Applicant: Delphi Technologies, Inc.

Inventor： Chavan, Abhijeet V. ,  Logsdon, James H. ,  Slaughter, Deron K. ,  Donahue, Michael P.

IPC: G01J5/12

CPC classification number: G01J5/12