Abstract:
An improved vertical integrated circuit device package (10) that eliminates or reduces the need for wire bond connections and/or solder connections is provided. The package includes a vertical device (14) having electrodes (20,21) on opposite surfaces, and a compressed spring member (12c) that is used to establish compression electrical connections between the electrodes (20) and corresponding electrically conductive elements (24).
Abstract:
An electronic assembly (200,400,400A) includes a bare IC die or a leadless electronic component (406A) having at least one electrically conductive contact formed on a surface of the die (106,406) or the component (406A) and a leadframe (102) or a substrate (402,402A) having at least one electrically conductive trace. The conductive contact of the component (406A) is electrically and mechanically coupled to the conductive trace with a solder joint (108,408). The solder joint (108,408) includes a plurality of solid electrically conductive metal particles (110,410) having a substantially spherical shape and a diameter ranging from about one mil to about ten mils.
Abstract:
A method by which semiconductor wafers (10, 12) can be solder bonded to form a semiconductor device, such as a sensor with a micromachined structure (14). The method entails forming a solderable ring (18) on the mating surface of a device wafer (10), such that the solderable ring (18) circumscribes the micromachine (14) on the wafer (10). A solderable layer (20, 26, 28) is formed on a capping wafer (12), such that at least the mating surface (24) of the capping wafer (12) is entirely covered by the solderable layer (20, 26, 28). The solderable layer (20, 26, 28) can be formed by etching the mating surface (24) of the capping wafer (12) to form a recess (16) circumscribed by the mating surface (24), and then forming the solderable layer (26) to cover the mating surface (24) and the recess (16) of the capping wafer (12). Alternatively, the solderable layer (28) can be formed by depositing a solderable material to cover the entire lower surface of the capping wafer (12), patterning the resulting solderable layer (28) to form an etch mask on the capping wafer (12), and then to form the recess (16), such that the solderable layer (28) covers the mating surface (24) but not the surfaces of the recess (16).