公开(公告)号：FR3009131A1

公开(公告)日：2015-01-30

申请号：FR1457183

申请日：2014-07-25

Applicant: GEN ELECTRIC

Inventor： KASHYAP AVINASH SRIKRISHNAN ,  SANDVIK PETER MICAH ,  ZHOU RUI ,  LOSEE PETER ALMERN

IPC: H01L23/58

Abstract: Un système à semiconducteurs à intégration monolithique (100) est présenté. Le système à semiconducteurs. (100) comporte un substrat (110) contenant du silicium (Si), et un composant semiconducteur à base de nitrure de gallium (GaN) est construit sur le substrat (110). Le système à semiconducteurs (100) comporte en outre au moins une structure de suppression de tensions transitoires (STT) (130) construite dans ou sur le substrat (110), la structure de STT (130) étant électriquement au contact (140) du composant semiconducteur à base de GaN (120). La structure de STT (130) est conçue pour fonctionner en mode pénétration, en mode avalanche ou dans des modes combinant ces deux derniers quand une tension appliquée dans le composant semiconducteur à base de GaN (120) dépasse une tension de seuil. Des procédés pour fabriquer un système à semiconducteurs à intégration monolithique (100) sont également présentés.

公开(公告)号：CA2544939A1

公开(公告)日：2005-06-09

申请号：CA2544939

申请日：2004-10-12

Applicant: GEN ELECTRIC

Inventor： TILAK VINAYAK ,  TUCKER JESSE ,  SANDVIK PETER MICAH ,  WOODMANSEE MARK ALLEN ,  MANIVANNAN VENKATESAN ,  LEMMON JOHN PATRICK ,  SHADDOCK DAVID MULFORD ,  MALE JONATHAN LLOYD ,  HAITKO DEBORAH ANN ,  WEAVER STANTON EARL

IPC: G01N27/414 ,  G01N33/00

公开(公告)号：AU2003299899A1

公开(公告)日：2004-07-29

申请号：AU2003299899

申请日：2003-12-22

Applicant: GEN ELECTRIC

Inventor： EVELYN MARK PHILLIP D ,  PARK DONG-SIL ,  LEBOEUF STEVEN FRANCIS ,  ROWLAND LARRY BURTON ,  NARANG KRISTI JEAN ,  HONG HUICONG ,  SANDVIK PETER MICAH

IPC: C30B9/00 ,  C30B25/02 ,  H01L21/205 ,  H01L21/331 ,  H01L21/335 ,  H01L29/20 ,  H01L29/732 ,  H01L29/737 ,  H01L29/778 ,  H01L33/32 ,  H01L21/20 ,  H01L21/02 ,  C30B25/20 ,  C30B29/40 ,  C30B9/12

Abstract: A device which includes at least one epitaxial semiconductor layer disposed on a single crystal substrate comprised of gallium nitride having a dislocation density less than about 10 4 per cm 2 , substantially no tilt boundaries, and an oxygen impurity level of less than 10 19 cm -3 . The electronic device may be in the form of lighting applications such as light emitting diode (LED) and laser diode (LD) applications and devices such as GaN based transistors, rectifiers, thyristors, and cascode switches, and the like. Also provided is a method of forming a single crystal substrate comprised of gallium nitride having a dislocation density less than about 10 4 per cm 2 , substantially no tilt boundaries, and an oxygen impurity level of less than 10 19 cm -3 , and homoepitaxially forming at least one semiconductor layer on the substrate and an electronic device.

公开(公告)号：CA2856490C

公开(公告)日：2018-02-13

申请号：CA2856490

申请日：2014-07-10

Applicant: GEN ELECTRIC

Inventor： KASHYAP AVINASH SRIKRISHNAN ,  SANDVIK PETER MICAH ,  ZHOU RUI ,  LOSEE PETER ALMERN

IPC: H01L21/71 ,  H01L23/62 ,  H01L29/20

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch- through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

公开(公告)号：CA2856490A1

公开(公告)日：2015-01-25

申请号：CA2856490

申请日：2014-07-10

Applicant: GEN ELECTRIC

Inventor： KASHYAP AVINASH SRIKRISHNAN ,  SANDVIK PETER MICAH ,  ZHOU RUI ,  LOSEE PETER ALMERN

IPC: H01L21/71 ,  H01L23/62 ,  H01L29/20

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

公开(公告)号：BR102012025930A2

公开(公告)日：2014-03-18

申请号：BR102012025930

申请日：2012-10-10

Applicant: GEN ELECTRIC

Inventor： KASHYAP AVINASH SRIKRISHNAN ,  SHADDOCK DAVID MULFORD ,  SANDVIK PETER MICAH ,  ARTHUR PSTEPHEN DALEY ,  TILAK VINAYAK

IPC: H02H1/04 ,  H01L29/86 ,  H02H3/22

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly (218) and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die (302) in a mesa structure that includes a first layer (306) of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer (308) of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer (312) of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

公开(公告)号：CA2792591A1

公开(公告)日：2013-04-26

申请号：CA2792591

申请日：2012-10-18

Applicant: GEN ELECTRIC

Inventor： KASHYAP AVINASH SRIKRISHNAN ,  SHADDOCK DAVID MULFORD ,  ANDARAWIS EMAD ANDARAWIS ,  SANDVIK PETER MICAH ,  ARTHUR STEPHEN DALEY ,  TILAK VINAYAK

IPC: H02H9/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly (218) and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die (302) in a mesa structure that includes a first layer (306) of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer (308) of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer (312) of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.