公开(公告)号：US11901304B2

公开(公告)日：2024-02-13

申请号：US17323423

申请日：2021-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sunil K. Singh ,  Vibhor Jain ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  Johnatan A. Kantarovsky ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L23/57 ,  H01L23/573 ,  H01L2223/5442 ,  H01L2223/54433

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

公开(公告)号：US11749717B2

公开(公告)日：2023-09-05

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L21/763 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7841

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20230207639A1

公开(公告)日：2023-06-29

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L29/7786 ,  H01L29/66462 ,  H01L29/41766 ,  H01L29/42316 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11380622B2

公开(公告)日：2022-07-05

申请号：US16953441

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/00

Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US12119383B2

公开(公告)日：2024-10-15

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11916119B2

公开(公告)日：2024-02-27

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/41783 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/7786

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US11764258B2

公开(公告)日：2023-09-19

申请号：US17108543

申请日：2020-12-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Brett T. Cucci ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Claire E. Kardos ,  Sen Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

公开(公告)号：US11710655B2

公开(公告)日：2023-07-25

申请号：US17505963

申请日：2021-10-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anthony K. Stamper ,  Henry L. Aldridge, Jr. ,  Johnatan A. Kantarovsky ,  Jeonghyun Hwang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/763 ,  H01L21/761

CPC classification number: H01L21/76224 ,  H01L21/761 ,  H01L21/763 ,  H01L29/0649

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

公开(公告)号：US11437329B2

公开(公告)日：2022-09-06

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

公开(公告)号：US11177158B2

公开(公告)日：2021-11-16

申请号：US16800011

申请日：2020-02-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Henry L. Aldridge, Jr. ,  Johnatan A. Kantarovsky ,  Jeonghyun Hwang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/763

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.