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    Capacitor structure for integrated circuit and related methods
    2.
    发明授权
    Capacitor structure for integrated circuit and related methods 有权

    公开(公告)号：US11348867B2

    公开(公告)日：2022-05-31

    申请号：US17089775

    申请日：2020-11-05

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

    IPC: H01L23/522 ,  H01L49/02

    Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

    CAPACITOR STRUCTURE FOR INTEGRATED CIRCUIT AND RELATED METHODS
    3.
    发明申请
    CAPACITOR STRUCTURE FOR INTEGRATED CIRCUIT AND RELATED METHODS 有权

    公开(公告)号：US20220139819A1

    公开(公告)日：2022-05-05

    申请号：US17089775

    申请日：2020-11-05

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

    IPC: H01L23/522 ,  H01L49/02

    Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

    Capacitor structure with MIM layer over metal pillars
    5.
    发明授权
    Capacitor structure with MIM layer over metal pillars 有权

    公开(公告)号：US11211448B2

    公开(公告)日：2021-12-28

    申请号：US16704180

    申请日：2019-12-05

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Sunil K. Singh ,  Eswar Ramanathan

    IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

    Abstract: A capacitor structure for an integrated circuit (IC) is provided. The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal layer is positioned over and between the metal pillars. At least one contact is operatively coupled to a first metal pillar of the plurality of metal pillars. The metal-insulator-metal layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the metal-insulator-metal layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.

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