STRUCTURE INCLUDING RESISTOR NETWORK FOR BACK BIASING FET STACK

    公开(公告)号:US20230188131A1

    公开(公告)日:2023-06-15

    申请号:US17643567

    申请日:2021-12-09

    Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

    POLYSILICON RESISTOR WITH CONTINUOUS U-SHAPED POLYSILICON RESISTOR ELEMENTS AND RELATED METHOD

    公开(公告)号:US20220271116A1

    公开(公告)日:2022-08-25

    申请号:US17182415

    申请日:2021-02-23

    Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.

    SEMICONDUCTOR STRUCTURE WITH IN-DEVICE HIGH RESISTIVITY POLYCRYSTALLINE SEMICONDUCTOR ELEMENT AND METHOD

    公开(公告)号:US20220181501A1

    公开(公告)日:2022-06-09

    申请号:US17114554

    申请日:2020-12-08

    Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

Patent Agency Ranking