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公开(公告)号：GB2422487B
公开(公告)日：2007-05-02
申请号：GB0607210
申请日：2003-09-23
Applicant: HRL LAB LLC , RAYTHEON CO
Inventor： CHOW LAP-WAI , CLARK WILLIAM M JR , HARBISON GAVIN J , BAUKUS JAMES P
IPC: G06K19/073 , H01L23/58
Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
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公开(公告)号：GB2405531B
公开(公告)日：2006-04-12
申请号：GB0427115
申请日：2003-05-06
Applicant: HRL LAB LLC , RAYTHEON CO
Inventor： CHOW LAP-WAI , CLARK WILLIAM M JR , BAUKUS JAMES P
IPC: H01L21/331 , H01L27/02 , H01L21/822 , H01L21/8238 , H01L21/8247 , H01L23/58 , H01L27/04 , H01L27/092 , H01L27/115 , H01L29/732 , H01L29/78 , H01L29/788 , H01L29/792
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公开(公告)号：GB2412240A
公开(公告)日：2005-09-21
申请号：GB0512203
申请日：2005-06-15
Applicant: HRL LAB LLC , RAYTHEON CO
Inventor： CHOW LAP-WAI , CLARK JR WILLIAM M , BAUKUS JAMES P , HARBISON GAVIN J
IPC: H01L21/8238 , H01L27/02 , H01L29/76
Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
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14.发明专利
公开(公告)号：GB2391986A8
公开(公告)日：2005-06-15
申请号：GB0325521
申请日：2002-03-12
Applicant: HRL LAB LLC
Inventor： CLARK WILLIAM M JR , CHOW LAP-WAI , BAUKUS JAMES P
IPC: G11C17/18 , G06F12/14 , G11C7/12 , G11C7/18 , G11C7/24 , G11C16/02 , G11C16/22 , H01L21/8246 , H01L21/8247 , H01L27/02 , H01L27/10 , H01L27/112 , H01L27/115
Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
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公开(公告)号：AU2003284270A8
公开(公告)日：2004-05-13
申请号：AU2003284270
申请日：2003-10-16
Applicant: PROMTEK , HRL LAB LLC
Inventor： BAUKUS JAMES P , CHOW LAP-WAI , CLARK WILLIAM M JR , YANG PAUL OU
IPC: H01L23/04 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/58 , H01L27/02 , H01L29/40
Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
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Patent Agency Ranking
公开(公告)号：WO2004049443A2
公开(公告)日：2004-06-10
申请号：PCT/US0337654
申请日：2003-11-20
Applicant: HRL LAB LLC , CHOW LAP-WAI , CLARK WILLIAM M JR , HARBISON GAVIN J , BAUKUS JAMES P
Inventor： CHOW LAP-WAI , CLARK WILLIAM M JR , HARBISON GAVIN J , BAUKUS JAMES P
CPC classification number: H01L23/573 , H01L27/02 , H01L2924/0002 , H01L2924/00
Abstract: A technique for and structres for camouflaging an integrated circuit structure. A layer ofconductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
Abstract translation: 用于伪装集成电路结构的技术和结构。 设置具有受控轮廓的导电材料层，以在实际上该装置不可操作时提供类似于可操作装置的导电材料的假象边缘。
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17.发明申请INTEGRATED CIRCUITS PROTECTED AGAINST REVERSE ENGINEERING USING AN APPARENT METAL CONTACT LINE TERMINATING ON FIELD OXIDE AND METHOD 审中-公开使用金属接触线终止氧化物和方法对反向工程进行保护的集成电路
公开(公告)号：WO02059968B1
公开(公告)日：2003-05-22
申请号：PCT/US0200123
申请日：2002-01-03
Applicant: HRL LAB LLC , CHOW LAP-WAI , BAUKAS JAMES P , CLARK WILLIAM M JR
Inventor： CHOW LAP-WAI , BAUKAS JAMES P , CLARK WILLIAM M JR
IPC: H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/10 , H01L29/76
CPC classification number: H01L23/573 , H01L27/0203 , H01L2924/0002 , H01L2924/00
Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprisingmetal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of thecircuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricatingsuch devices.
Abstract translation: 半导体器件，包括集成电路，防止逆向工程，包括导致场氧化物的金属轨迹。 金属化通常导致电路的栅极，源极或漏极区域，而不是绝缘场氧化物，从而误导逆向工程师。 一种用于制造这种装置的方法。
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18.发明申请INTEGRATED CIRCUITS PROTECTED AGAINST REVERSE ENGINEERING USING AN APPARENT METAL CONTACT LINE TERMINATING ON FIELD OXIDE AND METHOD 审中-公开使用金属接触线终止氧化物和方法对反向工程进行保护的集成电路
公开(公告)号：WO02059968A3
公开(公告)日：2002-11-14
申请号：PCT/US0200123
申请日：2002-01-03
Applicant: HRL LAB LLC , CHOW LAP-WAI , BAUKAS JAMES P , CLARK WILLIAM M JR
Inventor： CHOW LAP-WAI , BAUKAS JAMES P , CLARK WILLIAM M JR
IPC: H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/10 , H01L29/76
CPC classification number: H01L23/573 , H01L27/0203 , H01L2924/0002 , H01L2924/00
Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprisingmetal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of thecircuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricatingsuch devices.
Abstract translation: 半导体器件，包括集成电路，防止逆向工程，包括导致场氧化物的金属轨迹。 金属化通常导致电路的栅极，源极或漏极区域，而不是绝缘场氧化物，从而误导逆向工程师。 一种用于制造这种装置的方法。
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公开(公告)号：GB2451359B
公开(公告)日：2009-05-20
申请号：GB0816396
申请日：2005-06-07
Applicant: HRL LAB LLC
Inventor： SHU DAVID B , CHOW LAP-WAI , CLARK WILLIAM M JR
Abstract: An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.
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公开(公告)号：GB2449576B
公开(公告)日：2009-03-18
申请号：GB0814566
申请日：2005-06-07
Applicant: HRL LAB LLC
Inventor： SHU DAVID B , CHOW LAP-WAI , CLARK WILLIAM M JR
Abstract: An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.
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