公开(公告)号：JP2002041306A

公开(公告)日：2002-02-08

申请号：JP2001173506

申请日：2001-06-08

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/50 ,  G06F12/08 ,  G06F13/00 ,  G06F13/10 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/76 ,  G06F17/00

Abstract: PROBLEM TO BE SOLVED: To provide a logically separated data processing system in which a shared resource is emulated and individual copies of the shared resource are provided to each section. SOLUTION: The logically separated data processing system in this embodiment includes plural logical sections, plural operating systems to be operated in the data processing system and plural allocatable resources. Since each of the plural operating systems is allocated to independent one of the plural logical sections, two or more operating systems are not allocated to the given logical section. Each of the plural allocatable resources are allocated to one of the plural logical sections. In addition, the logically separated data processing system includes a hypervisor. The hypervisor emulates the shared resources such as an operator panel and a system console and provides virtual copies of the shared resources to each of the plural logical sections.

公开(公告)号：DE602007002628D1

公开(公告)日：2009-11-12

申请号：DE602007002628

申请日：2007-03-30

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS

IPC: G06F13/28

Abstract: A computer implemented method and system for migrating data accessible by input/output (I/O) devices using direct memory access. A request is received to migrate data. The data is migrated from a source page to a destination page in response to the request to migrate the data. Read data for the direct memory access are fetched from the source page. Write data for the direct memory access are stored in both the source page and the destination page.

公开(公告)号：DE69419680D1

公开(公告)日：1999-09-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：BR9403514A

公开(公告)日：1995-06-20

申请号：BR9403514

申请日：1994-09-12

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNDS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/20

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE2746779A1

公开(公告)日：1978-05-03

申请号：DE2746779

申请日：1977-10-18

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  MEYERHOFER JUN WILFRED LAWRENC ,  STEINBAUER DAVID MAX

IPC: G06K7/015 ,  G06K7/016 ,  G06K7/01 ,  G06K7/14

Abstract: A reader for badges having rows of data representative holes therethrough, the reader including a row of data reading photo-sensitive devices or the like for sensing light passing through a row of the badge holes, a stationary encoder bar having two rows of holes therethrough and a carriage movable with the badge as it is moved across the row of data reading devices for reading the holes in the badge and carrying a pair of control photo-sensitive devices for sensing light passing through the holes of the encoder bar. The holes in the two rows in the encoder bar are slightly staggered with respect to each other so as to provide main composite states in which the two control photo-sensitive devices are either both activated or inactivated and transition states in which just one of the two control photo-sensitive devices is activated, and means are provided responsive to the transition states for reading the data representative holes in the badge at the time of occurence of the transition states during movement of the badge and carriage.

公开(公告)号：DE102016222132A1

公开(公告)日：2017-05-18

申请号：DE102016222132

申请日：2016-11-10

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  AUERNHAMMER FLORIAN ALEXANDER

IPC: G06F9/48

Abstract: Eine Technik zum Verarbeiten von Interrupts in einem Datenverarbeitungssystem beinhaltet Empfangen einer Ereignisbenachrichtigungsnachricht (Event Notification Message, ENM) in einer Interrupt-Darstellungs-Steuereinheit (Interrupt Presentation Controller, IPC). Die ENM gibt eine Ebene, eine Ereigniszielnummer und eine Anzahl zu ignorierender Bits an. Die IPC ermittelt eine Gruppe virtueller Prozessor-Threads, die möglicherweise auf der Grundlage der Ereigniszielnummer, der Anzahl zu ignorierender Bits und einer Prozesskennung (ID) unterbrochen werden können, wenn die in der ENM angegebene Ebene einer Benutzerebene entspricht. Die Ereigniszielnummer kennzeichnet einen bestimmten virtuellen Prozessor-Thread, und die Anzahl zu ignorierender Bits kennzeichnet die Anzahl von Bits niedrigerer Ordnung, die in Bezug auf den betreffenden virtuellen Prozessor-Thread zu ignorieren sind, wenn eine Gruppe virtueller Prozessor-Threads ermittelt wird, die möglicherweise unterbrochen werden können.

公开(公告)号：BR0100999A

公开(公告)日：2002-02-13

申请号：BR0100999

申请日：2001-03-16

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/50 ,  G06F12/08 ,  G06F13/00 ,  G06F13/10 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/76 ,  G06F17/00

Abstract: A logically partitioned data processing system in which shared resources are emulated to provide each partition a separate copy of the shared resource is provided. In one embodiment, the logically partitioned data processing system includes a plurality of logical partitions, a plurality of operating systems executing within the data processing system and a plurality of assignable resources. Each of the plurality of operating systems is assigned to a separate one of the plurality of logical partitions, such that no more than one operating system is assigned to any given logical partition. Each of the plurality of assignable resources is assigned to a single one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor. The hypervisor emulates shared resources, such as an operator panel and a system console, and provides a virtual copy of these shared resources to each of the plurality of logical partitions.

公开(公告)号：DE2648078A1

公开(公告)日：1977-07-21

申请号：DE2648078

申请日：1976-10-23

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  TEAL THOMAS RICHARD

IPC: G06F13/00 ,  H04L7/06 ,  H04L12/423 ,  G06F3/02

Abstract: A self-clocking data entry unit system including a plurality of data entry units connected in seris in a loop which is connected at its ends to a controller. Data bits are provided by the controller flowing in one direction through the loop to each of the data entry units, and the data entry units supplant these data bits with new data bits which flow in the same direction through the loop back to the controller. Control bits are interspersed with the data bits, and each of the data bits has an accompanying tag bit that acts as a controlling bit but is of a different type than the first mentioned control bits so that there is a controlling bit of one type or another for each of the bit positions flowing through the loop for controlling the operation of the data entry units and maintaining their operation synchronized with the micro-controller.