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    12.
    发明专利
    未知

    公开(公告)号：BE773268A

    公开(公告)日：1972-03-29

    申请号：BE773268

    申请日：1971-09-29

    Applicant: IBM

    Inventor： BEAUSOLEIL W F

    IPC: G11C11/413 ,  G06F12/16 ,  G11C8/00 ,  G11C29/00 ,  G11C29/04 ,  G11C

    Abstract: 1311221 Digital data storage INTERNATICNAL BUSINESS MACHINES CORP 19 May 1971 [30 Sept 1970] 15759/71 Heading G4C A store comprises a number of units each containing a plurality of bit cells, corresponding cells from each unit storing a word, and the units are arranged so that bit cells which are known to be defective are situated in corresponding notional areas of the units, these areas being excluded from the addresses supplied by a system-store address translator. A memory may be made up from circuit cards each of which carries a plurality of modules, each module comprising four chips and each chip being divided into four notional quadrants. In manufacture, chips which are known to have defective cells in the same one, two or three quadrants are placed in the same chip position on the modules to form full-, half-, quarter- or three-quarter-size memories. For example, two ¢-size and four ¥-size memories may be combined to form a memory having a usable capacity four times that of a single perfect memory, the addressing circuitry being arranged to address non-defective words in a contiguous sequence of addresses, defective words occupying addresses notionally higher than the sequence.

    14.
    发明专利
    未知

    公开(公告)号：SE391056B

    公开(公告)日：1977-01-31

    申请号：SE1399472

    申请日：1972-10-30

    Applicant: IBM

    Inventor： BEAUSOLEIL W F

    IPC: G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C11/34

    Abstract: A monolithic computer memory constructed of monolithic chips which contain defective bit cells. During the production process, the chips are sorted into groups in accordance with the chip sector or quadrant which contains one or more defective cells. The chips are then mounted on modules and the modules are placed on memory cards, with all of the chips having a defect in a given chip sector being mounted in a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The valid cells are logically arranged in contiguous address locations by transformation logic which converts the address before it is presented to the memory bit cards. Addresses presented to the logic are re-ordered such that all addresses that, untranslated, would have selected a defective area of a chip, after being translated select a non-defective area of a chip.

    16.
    发明专利
    未知

    公开(公告)号：SE383427B

    公开(公告)日：1976-03-08

    申请号：SE1638071

    申请日：1971-12-21

    Applicant: IBM

    Inventor： BEAUSOLEIL W F ,  HO I T ,  PRICER W D

    IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/06

    Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

    18.
    发明专利
    未知

    公开(公告)号：BE761086R

    公开(公告)日：1971-05-27

    申请号：BE761086

    申请日：1970-12-30

    Applicant: IBM

    Inventor： BEAUSOLEIL W F

    IPC: G11C19/00 ,  G11C19/18 ,  G06F

    Abstract: An electronic bulk storage having the characteristics of a sequential access storage device. Data are stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feed-back loop for recirculating data and when selected, a group of elements at an address N is read in parallel a word at a time by electronically rotating data bits stored in the selected memory elements at an address. Controls are provided to select memory elements N+1 whenever elements at address N are selected by the selection matrix. First data is read out of the elements at address N and then data is read out of the elements at address N+1 without any time lost for reselection of memory elements.

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