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    3.
    发明专利
    未知

    公开(公告)号：BE805485A

    公开(公告)日：1974-01-16

    申请号：BE136192

    申请日：1973-09-28

    Applicant: IBM

    Inventor： CHANG C S ,  JEN T-S

    IPC: H01L21/331 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/73 ,  H01L29/78 ,  H01L

    Abstract: 1423183 Complentary field-effect transistors INTERNATIONAL BUSINESS MACHINES CORP 12 Sept 1973 [1 Nov 1972] 42856/73 Heading H1K In a complementary pair of field-effect transistors formed in a single semiconductor substate, each gate electrode comprises polycrystalline or amorphous silicon. doped with a P-type impurity and certain regions have specified impurity levels. In an embodiment, an N-type Si body 2 has a P-type pocket 8 formed therein (Fig. 1b) by ion implantation beneath a screening oxide layer 6. The screening layer 6 and the oxide layer 4 are removed and replaced by an overall oxide layer (10, Fig. 1c, not shown) causing drive-in of the P-type pocket 8. An N-type layer 12 of phosphorus is made by ion implantation after pocket 8 has been covered with photo-resist. The N- and the P-type regions (8, 12) are drivenin further by heating. A thick layer of oxide 14 is formed on the top surface and windows formed for the source, drain and other connections (Fig. le, not shown). A thin layer of oxide (16) is grown in the windows and overall covering (18) of silicon nitride formed followed by an overall covering (20) of polycrystalline silicon. The top of the silicon covering is oxidized and the oxide selectively removed then the silicon to leave the polycrystalline silicon gates 20 1 and 20 11 (Fig. 1g). Oxidation, photo-resist and etching techniques give a structure having uncovered areas which recieve boron by ion implantation to form P-type regions 23, 26, 28, the implantation also rendering the gates 20 1 , 20 11 P-type (Fig. 1j). An oxide film is provided over the gates and other P-type areas and subsequent steps provide diffused N-type zones (30, 32, 34, Fig. 1l, not shown). Two pairs of complementary field effect transistors may be made in a single substrate and connected to form a NAND gate (Figs. 2a, 2b and 3).

    4.
    发明专利
    未知

    公开(公告)号：SE389227B

    公开(公告)日：1976-10-25

    申请号：SE7314348

    申请日：1973-10-23

    Applicant: IBM

    Inventor： CHANG C S ,  JEN T-S

    IPC: H01L21/331 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/73 ,  H01L29/78

    Abstract: 1423183 Complentary field-effect transistors INTERNATIONAL BUSINESS MACHINES CORP 12 Sept 1973 [1 Nov 1972] 42856/73 Heading H1K In a complementary pair of field-effect transistors formed in a single semiconductor substate, each gate electrode comprises polycrystalline or amorphous silicon. doped with a P-type impurity and certain regions have specified impurity levels. In an embodiment, an N-type Si body 2 has a P-type pocket 8 formed therein (Fig. 1b) by ion implantation beneath a screening oxide layer 6. The screening layer 6 and the oxide layer 4 are removed and replaced by an overall oxide layer (10, Fig. 1c, not shown) causing drive-in of the P-type pocket 8. An N-type layer 12 of phosphorus is made by ion implantation after pocket 8 has been covered with photo-resist. The N- and the P-type regions (8, 12) are drivenin further by heating. A thick layer of oxide 14 is formed on the top surface and windows formed for the source, drain and other connections (Fig. le, not shown). A thin layer of oxide (16) is grown in the windows and overall covering (18) of silicon nitride formed followed by an overall covering (20) of polycrystalline silicon. The top of the silicon covering is oxidized and the oxide selectively removed then the silicon to leave the polycrystalline silicon gates 20 1 and 20 11 (Fig. 1g). Oxidation, photo-resist and etching techniques give a structure having uncovered areas which recieve boron by ion implantation to form P-type regions 23, 26, 28, the implantation also rendering the gates 20 1 , 20 11 P-type (Fig. 1j). An oxide film is provided over the gates and other P-type areas and subsequent steps provide diffused N-type zones (30, 32, 34, Fig. 1l, not shown). Two pairs of complementary field effect transistors may be made in a single substrate and connected to form a NAND gate (Figs. 2a, 2b and 3).

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