公开(公告)号：DE2713479A1

公开(公告)日：1977-10-06

申请号：DE2713479

申请日：1977-03-26

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  SILVERMAN RONALD

IPC: H01L27/10 ,  H01L21/033 ,  H01L21/316 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/265 ,  H01L27/00

Abstract: This describes a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers required in the prior art can be eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved.

公开(公告)号：DE2627827A1

公开(公告)日：1977-01-27

申请号：DE2627827

申请日：1976-06-22

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  JOSHI MADHUKAR LAXMAN ,  KROLL CHARLES THOMAS ,  SILVERMAN DONALD

IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/3105 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/08

Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

公开(公告)号：DE2257649A1

公开(公告)日：1973-06-07

申请号：DE2257649

申请日：1972-11-24

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  DINKLAGE JOHN BULLARD

IPC: H01L21/66 ,  G01R31/26

Abstract: 1380287 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 6 Nov 1972 [30 Nov 1971] 51117/72 Heading H1K A method of stressing insulating layers, particularly gate oxides of IGFETS, on the surface of semi-conductor wafers to cause early failure of imperfect layers comprises subjecting the layers to a glow discharge and an electric field, preferably of between 1 and 4 Î 10 6 volts/ cm, for a tine, e.g. 30 mins., sufficient to break down imperfect layers. A magnetic field of between 40 and 70 gauss also may be advantageously applied in a direction perpendicular to the insulating surface during the glow discharge, and the wafer may also be heated to between 70 and 250‹ C. by means of a heated coil. The operation may take place in a bell jar containing a low pressure of argon or nitrogen, the wafer being placed below an energized cathode, on a grounded anode. The magnetic field may be applied by an electromagnet encircling the bell jar. The wafer may be of silicon, the layer being thermally grown silicon dioxide, or else of silicon nitride, gallium nitride or titanium dioxide.