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    PROCESS FOR PRODUCING A HIGH-DENSITY INTEGRATED READ-ONLY MEMORY
    1.
    发明专利
    PROCESS FOR PRODUCING A HIGH-DENSITY INTEGRATED READ-ONLY MEMORY 未知

    公开(公告)号：DE3071648D1

    公开(公告)日：1986-07-24

    申请号：DE3071648

    申请日：1980-07-24

    Applicant: IBM

    Inventor： FORTINO ANDREAS GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

    IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78

    Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

    3.
    发明专利
    未知

    公开(公告)号：DE2713479A1

    公开(公告)日：1977-10-06

    申请号：DE2713479

    申请日：1977-03-26

    Applicant: IBM

    Inventor： BHATTACHARYYA ARUP ,  SILVERMAN RONALD

    IPC: H01L27/10 ,  H01L21/033 ,  H01L21/316 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/265 ,  H01L27/00

    Abstract: This describes a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers required in the prior art can be eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved.

    5.
    发明专利
    未知

    公开(公告)号：FR2316740A1

    公开(公告)日：1977-01-28

    申请号：FR7615011

    申请日：1976-05-13

    Applicant: IBM

    Inventor： BHATTACHARYYA ARUP ,  JOSHI MADHUKAR L ,  KROLL CHARLES T ,  SILVERMAN RONALD

    IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/3105 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/04 ,  H01L21/72 ,  G11C11/40

    Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

    6.
    发明专利
    未知

    公开(公告)号：IT1150032B

    公开(公告)日：1986-12-10

    申请号：IT2368880

    申请日：1980-07-25

    Applicant: IBM

    Inventor： FORTINO ANDRES GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

    IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78 ,  H01C

    Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

    7.
    发明专利
    未知

    公开(公告)号：FR2346855A1

    公开(公告)日：1977-10-28

    申请号：FR7703516

    申请日：1977-02-01

    Applicant: IBM

    Inventor： BHATTACHARYYA ARUP ,  SILVERMAN RONALD

    IPC: H01L21/033 ,  H01L27/10 ,  H01L21/316 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/04

    Abstract: This describes a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers required in the prior art can be eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved.

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