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    12.
    发明专利
    未知

    公开(公告)号：DE69122937T2

    公开(公告)日：1997-05-07

    申请号：DE69122937

    申请日：1991-07-18

    Applicant: IBM

    Inventor： BONEVENTO FRANCIS MICHAEL ,  MANDESE ERNEST NELSON ,  MENDELSON RICHARD NEIL

    IPC: G06F13/24

    Abstract: This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus. An interrupt controller is coupled to the microprocessor and bus for recognising delivery of an interrupt signal and for periodically generating an interrupt reset signal and delivering reset signals to all of the input/output devices simultaneously for setting all of the devices to a condition indicative of no request for access to said microprocessor.

    APPARATUS AND METHOD FOR ASYNCHRONOUSLY DELIVERING CONTROL ELEMENTS WITH A PIPE INTERFACE
    14.
    发明专利
    APPARATUS AND METHOD FOR ASYNCHRONOUSLY DELIVERING CONTROL ELEMENTS WITH A PIPE INTERFACE 未知

    公开(公告)号：AU630493B2

    公开(公告)日：1992-10-29

    申请号：AU6130990

    申请日：1990-08-24

    Applicant: IBM

    Inventor： BONEVENTO FRANCIS MICHAEL ,  MCGOVERN JOSEPH PATRICK ,  THOMAS EUGENE MITCHELL

    IPC: G06F15/16 ,  G06F5/06 ,  G06F13/42 ,  G06F13/38

    Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

    COMPUTER COMMAND INTERFACE
    15.
    发明专利
    COMPUTER COMMAND INTERFACE 未知

    公开(公告)号：NZ233824A

    公开(公告)日：1992-09-25

    申请号：NZ23382490

    申请日：1990-05-25

    Applicant: IBM

    Inventor： BONEVENTO FRANCIS MICHAEL ,  CHISHOLM DOUGLAS RODERICK ,  DODDS SAMMY DAVIS ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST NELSON ,  MCNEILL ANDREW BOYCE ,  MENDELSON RICHARD NEIL

    IPC: G06F13/12 ,  G06F13/00

    Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

    APPARATUS AND METHOD FOR ASYNCHRONOUSLY DELIVERING CONTROL ELEMENTS WITH A PIPE INTERFACE
    16.
    发明专利
    APPARATUS AND METHOD FOR ASYNCHRONOUSLY DELIVERING CONTROL ELEMENTS WITH A PIPE INTERFACE 未知

    公开(公告)号：AU6130990A

    公开(公告)日：1991-03-28

    申请号：AU6130990

    申请日：1990-08-24

    Applicant: IBM

    Inventor： BONEVENTO FRANCIS MICHAEL ,  MCGOVERN JOSEPH PATRICK ,  THOMAS EUGENE MITCHELL

    IPC: G06F15/16 ,  G06F5/06 ,  G06F13/42 ,  G06F13/38

    Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

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