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公开(公告)号：CA2161460C
公开(公告)日：1999-05-11
申请号：CA2161460
申请日：1990-03-16
Applicant: IBM
Inventor： BENEVENTO FRANCIS MICHAEL , CHILSHOLM DOUGLAS RODERICK , MANDESE ERNEST NELSON , MCNEILL ANDREW BOYCE , MENDELSON RICHARD NEIL , DODDS SAMMY DAVIS , DESAI DHRUVKUMAR M
IPC: G06F13/14
Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.
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公开(公告)号：CA2012400C
公开(公告)日：1999-03-30
申请号：CA2012400
申请日：1990-03-16
Applicant: IBM
Inventor： CHISHOLM DOUGLAS RODERICK , BONEVENTO FRANCIS MICHAEL , MENDELSON RICHARD NEIL , MCNEILL ANDREW BOYCE , MANDESE ERNEST NELSON , DESAI DHRUVKUMAR M , DODDS SAMMY DAVIDS
Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.
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公开(公告)号：DE69024111T2
公开(公告)日：1996-06-20
申请号：DE69024111
申请日：1990-06-11
Applicant: IBM
Inventor： DIXON JERRY DUANE , KEENER DON STEVEN , LOCKER HOWARD JEFFREY , MARAZAS GERALD ALLAN , MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , OSBORN NEAL ALLEN
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
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公开(公告)号：DE69023701D1
公开(公告)日：1996-01-04
申请号：DE69023701
申请日：1990-05-31
Applicant: IBM
Inventor： MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , OSBORN NEAL ALLEN , REID EDDIE MILLER
Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.
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公开(公告)号：CZ284019B6
公开(公告)日：1998-07-15
申请号：CS291790
申请日：1990-06-12
Applicant: IBM
Inventor： MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , OSBORN NEAL ALLEN , REID EDDIE MILLER
Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.
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Patent Agency Ranking
公开(公告)号：CA2092631C
公开(公告)日：1997-04-08
申请号：CA2092631
申请日：1993-03-12
Applicant: IBM
Inventor： KEENER DON STEVEN , MCNEILL ANDREW BOYCE , SCHEIERN KEVIN LEE , NEWSOM THOMAS HAROLD , VOORHEES RICHARD W , WACHTEL EDWARD IRVING
Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.
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公开(公告)号：HK71496A
公开(公告)日：1996-05-03
申请号：HK71496
申请日：1996-04-25
Applicant: IBM
Inventor： DIXON JERRY DUANE , KEENER DON STEVEN , LOCKER HOWARD JEFFREY , MARAZAS GERALD ALLAN , MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , OSBORN NEAL ALLEN
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
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公开(公告)号：NZ234712A
公开(公告)日：1993-04-28
申请号：NZ23471290
申请日：1990-07-30
Applicant: IBM
Inventor： BEALKOWSKI RICHARD , BLACKLEDGE JOHN WILEY , CRONK DOYLE STANFILL , DAYAN RICHARD ALAN , KINNEAR SCOTT GERARD , KOVACH GEORGE D , PALKA MATTHEW STEPHEN , SACHSENMAIER ROBERT , ZYVOLOSKI KEVIN MARSHALL , DIXON JERRY DUANE , MCNEILL ANDREW BOYCE , WACHTEL EDWARD IRVING
Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device (62) into a personal computer system (10). The personal computer system (JO) comprises a system processor (26), a system planar (24), a random access main memory (32), a read only memory (36), a protection means and at least one direct access storage device (62). The read only memory (36) includes a first portion of BIOS and data representing the type of system processor (26) and system planar (24) I/O configuration. The first portion of BIOS initializes the system (10) and the direct access storage device (62), and resets the protection means in order to read in a master boot record into the random access memory (32) from a protectable partition on the direct access storage device (62). The master boot record includes a data segment and an executable code segment. The data segment includes data representing system hardware and a system configuration which is supported by the master boot record. The first BIOS portion confirms the master boot record is compatible with the system hardware by verifying that the data from the data segment of the master boot record agrees with the system processor (26), system planar (24), and planar (24) I/O configuration. If the master boot record is compatible with the system hardware, the first BIOS portion vectors the system processor (26) to execute the executable code segment of the master boot record. The executable code segment confirms that the system configuration has not changed and loads in the remaining BIOS portion from the same protectable partition on the direct access storage device (62) into random access memory (32). The executable code segment then verifies the authenticity of the remaining BIOS portion and vectors the system processor (26) to begin executing the BIOS now in random access memory. BIOS, executing in random access memory (32), then activates the protection means to prevent further access to the protectable partition. BIOS boots up the operating system to begin operation of the personal computer system.
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公开(公告)号：IN186098B
公开(公告)日：2001-06-16
申请号：IN363DE1993
申请日：1993-04-13
Applicant: IBM
Inventor： KEENER DON STEVEN , MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , SCHEIERN KEVIN LEE , VOORHEES RICHARD W , WACHTEL EDWARD IRVING
IPC: G06F13/38
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公开(公告)号：DE69026018T2
公开(公告)日：1996-10-02
申请号：DE69026018
申请日：1990-09-11
Applicant: IBM
Inventor： KEENER DON STEVEN , MCNEILL ANDREW BOYCE , WACHTEL EDWARD IRVING
IPC: G06F13/362 , G06F13/22 , G06F13/24 , G06F13/374
Abstract: Apparatus and method for increasing efficiency of command execution from a host processor (11) over an SCSI bus (14). Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine (32). Additional protocol functions are implemented in a foreground state machine (26). When the host processor (11) issues a command for access to the SCSI bus (14), the background state machine (32) can be programmed before the foreground machine (26) completes the protocol function for a previous command. Thus, the background state machine (32) is ready to arbitrate for access to the bus (14) at the very next bus free condition.
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