公开(公告)号：GB2368461A

公开(公告)日：2002-05-01

申请号：GB0113679

申请日：2001-06-06

Applicant: IBM

Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423

Abstract: A method for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric, e.g. an oxide, layer 20 over a substrate 10, forming a sacrificial layer 21,30 over the gate dielectric layer, forming first openings (32, fig 3) through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric 40 having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor 60 above the first gate dielectric in the first openings, forming a second opening (71, fig 7) through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor 81 in the second opening. Source and drain regions may be formed before or after the gates. This process allows the gate dielectrics to be formed without direct contact with resists. The gate dielectrics are therefore free of photoresists impurities.

公开(公告)号：DE69636244T2

公开(公告)日：2007-04-26

申请号：DE69636244

申请日：1996-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRONNER GARY B ,  HANSCH WILFRIED ,  NOBLE WENDELL P

IPC: H01L21/8242 ,  H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L27/108

Abstract: A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.

公开(公告)号：DE69636244D1

公开(公告)日：2006-07-27

申请号：DE69636244

申请日：1996-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRONNER GARY B ,  HANSCH WILFRIED ,  NOBLE WENDELL P

IPC: H01L21/8242 ,  H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L27/108

Abstract: A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.

公开(公告)号：DE69220543T2

公开(公告)日：1998-01-15

申请号：DE69220543

申请日：1992-04-11

Applicant: IBM

Inventor： BRONNER GARY B ,  DHONG SAN H ,  HWANG WEI

IPC: H01L21/8242 ,  H01L21/76 ,  H01L27/10 ,  H01L27/108

Abstract: Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor (28, 32, 34) disposed in a trench (28) formed in a semiconductor substrate (24, 30) and an access transistor (12) disposed in a well (18) which is opposite in conductivity type to that of the substrate (24, 30) and a buried oxide collar (36) which surrounds an upper portion of the trench (28).