公开(公告)号：EP2433303A4

公开(公告)日：2014-09-17

申请号：EP09845033

申请日：2009-05-22

Applicant: IBM

Inventor： FILIPPI RONALD ,  STANDAERT THEODORUS E ,  GRUNOW STEPHAN ,  SANKARAN SUJATHA ,  CHANDA KAUSHIK ,  GAMBINO JEFFREY P ,  SIMON ANDREW H ,  HU CHAO-KUN ,  BONILLA GRISELDA

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1839338A4

公开(公告)日：2011-11-09

申请号：EP05854112

申请日：2005-12-14

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

公开(公告)号：EP1671358A4

公开(公告)日：2009-10-21

申请号：EP04789450

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1687850A4

公开(公告)日：2008-06-25

申请号：EP04779326

申请日：2004-07-28

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

IPC: H01L23/28 ,  H01L20060101 ,  H01L21/301 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop (28) for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal (12) is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

公开(公告)号：JP2010157704A

公开(公告)日：2010-07-15

申请号：JP2009271765

申请日：2009-11-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  PETRARCA KEVIN S ,  FAROOQ MUKTA G ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/866

CPC classification number: H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-metal capacitor having improved manufacturing possibility, and to provide a method for fabricating the same. SOLUTION: A semiconductor structure including the vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的制造可能性的金属 - 绝缘体 - 金属电容器，并提供其制造方法。 解决方案：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用来自虚设金属氧化物半导体场效应晶体管的结构部件 并且形成在位于半导体衬底上方的隔离区域上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：EP2020023A4

公开(公告)日：2012-09-19

申请号：EP07761307

申请日：2007-04-26

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

公开(公告)号：EP1817801A4

公开(公告)日：2010-07-28

申请号：EP05851917

申请日：2005-11-18

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  STAMPER ANTHONY K

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

公开(公告)号：EP1584108A4

公开(公告)日：2006-06-07

申请号：EP03701269

申请日：2003-01-08

Applicant: IBM

Inventor： MANDELMAN JACK A ,  GAMBINO JEFFREY P ,  WANG GENG

IPC: H01L21/20 ,  H01L21/308 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

公开(公告)号：WO2013089938A2

公开(公告)日：2013-06-20

申请号：PCT/US2012063508

申请日：2012-11-05

Applicant: IBM

Inventor： ADKISSON JAMES W ,  DUNBAR THOMAS J ,  GAMBINO JEFFREY P ,  LEITCH MOLLY J

IPC: H01L29/78 ,  B82Y99/00 ,  H01L21/336

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: Manufacturing a semiconductor structure (5) including: forming a seed material (25) on a sidewall of a mandrel (20a, 20b); forming a graphene field effect transistor (FET) (30) on the seed material (25); and removing the seed material (25).

Abstract translation: 制造半导体结构（5），包括：在心轴（20a，20b）的侧壁上形成种子材料（25）; 在种子材料（25）上形成石墨烯场效应晶体管（FET）（30）; 并除去种子材料（25）。

公开(公告)号：JP2010212668A

公开(公告)日：2010-09-24

申请号：JP2010025483

申请日：2010-02-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JAFFE MARK D ,  GAMBINO JEFFREY P ,  ELLIS-MONAGHAN JOHN JOSEPH ,  RASSEL RICHARD JOHN

IPC: H01L27/146 ,  H01L27/14 ,  H04N5/335 ,  H04N101/00

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

Abstract: PROBLEM TO BE SOLVED: To provide CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells, and design structures for fabricating the pixel sensor cells. SOLUTION: The CMOS image sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within each pixel sensor cell. In a first particular generalized embodiment, a light blocking layer is located and formed interposed between a first semiconductor layer including a photoactive region and a second semiconductor layer including at least a second transistor or a floating diffusion region shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of the floating diffusion region, and are arranged, shielded in a dielectric-isolated metallization stack over a carrier substrate. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法以及用于制造像素传感器单元的设计结构。 解决方案：CMOS图像传感器单元被设计成通过在每个像素传感器单元内提供来自至少一个晶体管的背面照明的光屏蔽来允许在全局快门模式中进行背面照明。 在第一特定广义实施例中，遮光层位于包括光活性区域的第一半导体层和至少包括第二晶体管或由遮光层屏蔽的浮动扩散区域的第二半导体层之间并形成。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散区域，并且被布置成在载体衬底上的介电隔离金属化堆叠中被屏蔽。 版权所有（C）2010，JPO＆INPIT