公开(公告)号：JP2000082800A

公开(公告)日：2000-03-21

申请号：JP22931499

申请日：1999-08-13

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  KAARU JIEI RADENSU ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To form a buried strap through a simplified process by a structure wherein the part of second conductive material positioned between the depth of a strap and the upper surface of a trench includes a buried strap. SOLUTION: The method for forming a strap comprises a step for making a trench 200 in a substrate 201, a step for filling the trench 200 partially with a first conductive material 202, and a step for applying a color material 203 to the part of the trench 200 on the first conductive material 202. The method further comprises a step for etching the color material 203 down to the depth of a strap 205 beneath the upper surface of the trench 200, and a step for filling the trench 200 with a second conductive material 210. The part of second conductive material 210 positioned between the depth of the strap 205 and the upper surface of the trench 200 is formed while including the buried strap. 205.

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：JPH11274427A

公开(公告)日：1999-10-08

申请号：JP3117299

申请日：1999-02-09

Applicant: Internatl Business Mach Corp ,  Toshiba Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション ,  株式会社東芝

Inventor： KLEINHENZ RICHARD L ,  BRONNER GARY B ,  IBA JUNICHIRO

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/1087

Abstract: PROBLEM TO BE SOLVED: To form an embedded plate electrode of a trench capacitor of a semiconductor memory cell with ease in a simple process.
SOLUTION: A dopant source film 114 is formed on a side wall and a bottom part of a trench 112 formed in a semiconductor substrate 100, and on the dopant source film a resist 116 is formed, which covers the trench 112. A recessed part is formed at the resist 116 so that the resist 116 in the trench 112 remains lower than the surface of the semiconductor substrate 100, and impurities are injected into the semiconductor substrate with the resist 116 as a mask. With the resist 116 as a mask, the dopant source film 114 is etched to remove the remaining resist 116, and the dopant is diffused from the impurities and the dopant source film 114 into the semiconductor substrate 100 to form an embedded plate electrode.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：以简单的方法容易地形成半导体存储单元的沟槽电容器的嵌入式板电极。 解决方案：在形成在半导体衬底100中的沟槽112的侧壁和底部形成掺杂剂源膜114，并且在掺杂剂源膜上形成覆盖沟槽112的抗蚀剂116.凹部是 形成在抗蚀剂116处，使得沟槽112中的抗蚀剂116保持低于半导体衬底100的表面，并且以抗蚀剂116作为掩模将杂质注入到半导体衬底中。 以抗蚀剂116作为掩模，蚀刻掺杂剂源膜114以除去剩余的抗蚀剂116，并且掺杂剂从杂质和掺杂剂源膜114扩散到半导体衬底100中以形成嵌入的板电极。

公开(公告)号：JPH11265985A

公开(公告)日：1999-09-28

申请号：JP10499

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P ,  KOTECKI DAVID E

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming the patterned metal electrode when the metal itself is hard to etch. SOLUTION: The pattern of the metal than is hard to etch is formed by converting the metal that is hard to etch into a plurality of metal components that can be etched in the region, wherein the metal than is hard to etch is removed. This method includes the step, which attaches a metal layer 8 that is hard to etch on a sacrifice metal composition layer 7 and an exposed region, the step, which forms a plurality of metal compositions that can be etched by the reaction of the sacrifice metal composition layer 7 and the metal 8 that is hard to etch, and the step, which selectively removes the plurality of the metal compositions that can be etched and makes to remain the patterned metal layer that is hard to etch on the surface.

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：JPH11251429A

公开(公告)日：1999-09-17

申请号：JP3199

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide an improved damascene process for forming an interconnect to a conductive stud. SOLUTION: An electrical connection to a stud is made by filling a conductive stud material in a contact hole formed in a dielectric material layer 7, patterning the conductive stud material, removing a shallow part of the dielectric material layer surrounding the conductive stud material, depositing a second dielectric material layer 9, forming a trench in the second dielectric material layer in an upper region of the conductive stud, and patterning a conductive material in the trench.

公开(公告)号：JPH09186301A

公开(公告)日：1997-07-15

申请号：JP34589896

申请日：1996-12-25

Applicant: SIEMENS AG ,  IBM

Inventor： BRONNER GARY B ,  HANSCH WILFRIED ,  NOBLE WENDELL P

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To make the formation of buried capacitor electrodes, which can be reconciled with the formation of a large-capacity DRAM, possible at low cost and with a high productivity by a method wherein epitaxial layers, which respectively cover a region containing impurities implanted therein and consist of a semiconductor material, are grown and the impurities are diffused in the epitaxial layers. SOLUTION: As an example, a trench capacitor structure is used as an original boundary of an implantation region 20 and the boundary 48 between buried electrodes attained by diffusion. Trenches 4 respectively end in the buried electrodes and the insulation of the trenches from a substrate is obtained by the boundary between the electrodes lower than those to correspond to the respective valleys of dopant profile valleys. Oxide-nitride-oxide sandwich capacitor dielectric materials 52 are respectively formed in the interiors of the trenches 46. Another connection of a dynamic random access memory device can be formed by a metallization, which can form even conductive terminals of transistors 58 and 58' which are used for controlling an access to a cell.

公开(公告)号：DE69220543D1

公开(公告)日：1997-07-31

申请号：DE69220543

申请日：1992-04-11

Applicant: IBM

Inventor： BRONNER GARY B ,  DHONG SAN H ,  HWANG WEI

IPC: H01L21/8242 ,  H01L21/76 ,  H01L27/10 ,  H01L27/108

Abstract: Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor (28, 32, 34) disposed in a trench (28) formed in a semiconductor substrate (24, 30) and an access transistor (12) disposed in a well (18) which is opposite in conductivity type to that of the substrate (24, 30) and a buried oxide collar (36) which surrounds an upper portion of the trench (28).

公开(公告)号：CA2130978C

公开(公告)日：1997-09-30

申请号：CA2130978

申请日：1994-08-26

Applicant: IBM

Inventor： KENNEY DONALD M ,  BRONNER GARY B ,  DEBROSSE JOHN K

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：GB2368461B

公开(公告)日：2004-09-08

申请号：GB0113679

申请日：2001-06-06

Applicant: IBM

Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423

Abstract: A method and structure for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.