公开(公告)号：JP2001222465A

公开(公告)日：2001-08-17

申请号：JP2000390789

申请日：2000-12-22

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  JENKINS STEVEN KENNETH ,  SIEGEL MICHAEL STEVEN ,  MICHAEL RAYMOND TROMBLAY ,  VERPLANKEN FABRICE JEAN

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/16 ,  G06F15/167 ,  G11C11/407 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To improve the capacity of a network processor for moving data to a dynamic random access memory(DRAM) chip to be used for a computer system or moving data from the chip. SOLUTION: Two double data rate DRAMs are used in order to double band width in accordance with the throughput of increased data. The movement of data is further improved by setting up complete reading of four banks and complete writing of four banks by a network processor in each repeat of a DRAM time clock. A scheme for reading and writing accesses randomized by the network processor is discloses. The scheme can be applied especially to a network such as the Ethernet (R) using various frame sizes.

公开(公告)号：JP2006020371A

公开(公告)日：2006-01-19

申请号：JP2005282931

申请日：2005-09-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO C ,  RAO SRIDHAR ,  SIEGEL MICHAEL STEVEN ,  YOUNGMAN BRIAN ALAN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  H04L12/56 ,  G06F13/40 ,  G06F15/177

CPC classification number: H04L49/3036 ,  G06F13/4022 ,  H04L49/15 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351

Abstract: PROBLEM TO BE SOLVED: To provide a scalable switch architecture which is used in data communication network, increases processing speed of transferred data, and can resize support capability into within a scope of each type of potential request. SOLUTION: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在数据通信网络中使用的可扩展交换机架构，提高传输数据的处理速度，并且可以将支持能力调整到每种类型的潜在请求的范围内。 解决方案：一种网络交换设备，用于这种设备的部件，以及操作这样的设备的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性 。 控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令中与包括可选交换结构设备在内的其他元件协作。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003273741A

公开(公告)日：2003-09-26

申请号：JP2003045493

申请日：2003-02-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CALVIGNAC JEAN LOUIS ,  LYNCH JEFFREY JAMES ,  VERPLANKEN FABRICE JEAN

IPC: H03M7/12 ,  H03M7/00 ,  H03M7/14 ,  H03M9/00

CPC classification number: H03M7/14 ,  H03M9/00

Abstract: PROBLEM TO BE SOLVED: To provide many independent bit patterns on a 2-bit status channel without changing the characteristic of the 2-bit status channel such as changing a '11' synchronization bit pattern.
SOLUTION: A scalable interface including a plurality of 2-bit transmission channels is explained. An encoder divides a digital stream into 3 bits, these 3 bits are encoded to 4 bits, and the respective pairs of the bits of respective 4-bit patterns are transmitted via a back-to-back clock cycle on separate channels.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：在2位状态通道上提供许多独立的位模式，而不改变2位状态通道的特性，例如改变“11”同步位模式。 解释说明了包括多个2位传输信道的可伸缩接口。 一个编码器将数字流分成3位，这3位被编码为4位，相应的4位模式的各个位对通过单独通道的背对背时钟周期传送。 版权所有（C）2003，JPO

公开(公告)号：JP2001357071A

公开(公告)日：2001-12-26

申请号：JP2001091839

申请日：2001-03-28

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  ANTONIOS MARAGUKOSU ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F17/30 ,  H04L12/46 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide novel data structure, method and device for finding out full matching(FM) between a search pattern and a pattern stored in the leaf of a search tree. SOLUTION: A key is inputted, a hash function is executed to a key, a direct table(DT) is accessed, and walk-through of the tree is performed until reaching the leaf through a pattern search control block(PSCB). Both the key and correspondent information required for retrieval are stored in a Patricia tree structure and the hash function performs mapping of n->n from the bit of the key to the bit of a hashed key.

公开(公告)号：MY125746A

公开(公告)日：2006-08-30

申请号：MYPI20030638

申请日：2003-02-25

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  LYNCH JEFFREY JAMES ,  VERPLANKEN FABRICE JEAN

IPC: H03M7/14 ,  H03M7/00 ,  H03M9/00 ,  H03M7/12

Abstract: DESCRIBED IS A SCALABLE INTERFACE INCLUDING A PLURALITY OF 2-BIT TRANSMISSION CHANNELS.AN ENCODER PARTITIONS A DIGITAL BIT STREAM INTO 3 BITS WHICH ARE CODED INTO 4 BITS WITH EACH PAIR OF BITS IN EACH 4 BIT PATTERN TRANSMITTED VIA BACK-TO-BACK CLOCK CYCLES ON SEPARATE ONES OF THE CHANNELS.(FIGURE 2A-C)

公开(公告)号：AT293864T

公开(公告)日：2005-05-15

申请号：AT02712095

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  PARK WINCHESTER ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/56

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

公开(公告)号：ES2226958T3

公开(公告)日：2005-04-01

申请号：ES00983409

申请日：2000-12-21

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.

公开(公告)号：HU0303240A2

公开(公告)日：2003-12-29

申请号：HU0303240

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/861 ,  H04L29/06

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

公开(公告)号：AU2002347376A8

公开(公告)日：2003-07-09

申请号：AU2002347376

申请日：2002-12-09

Applicant: IBM

Inventor： VERPLANKEN FABRICE JEAN ,  CALVIGNAC JEAN LOUIS

IPC: H04L12/56 ,  G06F17/30 ,  H04L12/46

Abstract: A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.

公开(公告)号：AU2002232002A1

公开(公告)日：2002-09-12

申请号：AU2002232002

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  LOGAN JOSEPH FRANKLIN ,  HEDDES MARCO ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/861 ,  H04L29/06

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.