公开(公告)号：SG194196A1

公开(公告)日：2013-11-29

申请号：SG2013076872

申请日：2012-05-03

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS ,  CANDELARIA SUSAN KAY

Abstract: A computer program product is configured for performing a method including: generating at least one command message by a channel subsystem of the host computer system, the at least one command message including one or more device command words (DCWs), wherein at least one DCW of the one or more DCWs includes a suppress-length indication (SLI) configured to instruct a control unit to continue to perform the I/O operation in response to the control unit detecting that the data count does not match an amount of data required; receiving an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required; and responsive to receiving the IL value from the control unit, storing an IL indicator in a subchannel-status word.

公开(公告)号：GB2491438A

公开(公告)日：2012-12-05

申请号：GB201206682

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38

Abstract: Method for input/output (I/O) between host computer and control-unit 118, comprising: generating and storing in local memory 132 address control words specifying host memory 106 locations for data transfer and data check word generation and save field; responsive to data transfer requests including data to be stored in host memory and data check word, storing data-check-word in save field, and checking data corruption; responsive to data-transfer requests for data to be retrieved from host memory, generating data-check-words based on generation field and appending data-check-words to data. Data-check-words include: longitudinal (LRC)/ cyclical (CRC) redundancy check-word and checksum. I/O can be transport mode. I/O start rates are increased and response time reduced by providing data router 160 in channel of a channel subsystem allowing host bus adaptor (HBA) 154 to directly access host memory without storing I/O data in channel. Isolation for error checking and addressing of multiple address spaces is provided.

公开(公告)号：DE69028462T2

公开(公告)日：1997-03-27

申请号：DE69028462

申请日：1990-06-23

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN RICHARD ,  MIRACLE GERALD HOLT ,  NEUNER RICHARD ANDREW ,  POTVIN PETER LLOYD

IPC: G06F13/12

Abstract: A device control unit (19) operating under the protocol of a parallel bus (24) is connected by a serial link (18, 20) to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit (22) interconnects the parallel bus (24) and the serial link (18, 20) and performs the specific operations of the parallel bus protocol. The channel and the extender unit (22) send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features. New operations using the protocol reduce the delays that would otherwise be required in the communications between the channel and the extender unit. The serial link (18, 20) can be made longer when the delays are reduced.

公开(公告)号：DE69029643D1

公开(公告)日：1997-02-20

申请号：DE69029643

申请日：1990-10-06

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN RICHARD ,  GREGG THOMAS ANTHONY ,  KALOS MATTHEW JOSEPH ,  LIENCRES BJORN

IPC: H04L29/08 ,  G06F13/12 ,  H04L29/06 ,  G06F13/38 ,  G06F13/42

Abstract: An outbound frame state machine (OFSM) which generates data frames for transmission over a data link. The outbound frame state machine (OFSM) is microcode controlled and includes an outbound frame header buffer (60) for containing information to be included in the header of the frame, a data buffer (26) for storing data characters to be included in the data frame, a data generator register (98) for providing special sequences of data characters, if required, and an outbound frame trace buffer for storing a trace log of all frames transmitted in the normal mode and to be used if the outbound frame state machine (OFSM) is operating in the simulated I/O mode or the diagnostic mode. In the normal mode of operation, the outbound frame state machine (OFSM) builds a data frame using header information from the frame header buffer, and may include data from the data buffer, all as specified by control bits stored in a control register. The control register may also include a bit for causing special sequences to be transmitted. In the simulation mode, frames are built by the outbound frame state machine (OFSM) and then wrapped back to the channel to be processed like frames from a control unit. In the diagnostic mode, the outbound frame state machine (OFSM) inserts various characters into the outbound data bit stream to create possible error situations on the data link.

公开(公告)号：MX354282B

公开(公告)日：2018-02-21

申请号：MX2013011408

申请日：2012-04-11

Applicant: IBM

Inventor： CARLSON SCOTT ,  FLANAGAN JOHN ,  RIEDY DALE ,  HATHORN ROGER ,  YUDENFRIEND HARRY ,  KALOS MATTHEW JOSEPH ,  CASPER DANIEL FRANCIS ,  LOUIS WILLIAM RICCI

IPC: G06F13/42

Abstract: Se proporciona un producto de programa de computadora para realizar: envío, por un subsistema de canal, de un mensaje de solicitud de entrada en el sistema de proceso (PRLI) a la unidad de control que indica si el subsistema de canal soporta transferencia de datos bidireccional; recibir un mensaje de respuesta PRLI de la unidad de control que indica si la unidad de control soporta transferencia de datos bidireccional; recolectar una pluralidad de comandos, al menos unos de los cuales especifica una transferencia de datos de entrada y al menos uno que especifica una transferencia de datos de salida, enviar al menos un mensaje de datos de salida a la unidad de control que incluye datos de salida a transferir a la unidad de control, el mensaje de datos de salida asociado con al menos una de la pluralidad de comandos que especifica una transferencia de datos de salida; y recibir al menos un mensaje de entrada de la unidad de control que incluye datos de entrada para guardar en un almacenamiento principal del sistema de computadora anfitrión.

公开(公告)号：AU2012278232B2

公开(公告)日：2015-08-20

申请号：AU2012278232

申请日：2012-05-03

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS ,  CANDELARIA SUSAN KAY

IPC: G06F13/12

Abstract: A computer program product is configured for performing a method including: generating at least one command message by a channel subsystem of the host computer system, the at least one command message including one or more device command words (DCWs), wherein at least one DCW of the one or more DCWs includes a suppress-length indication (SLI) configured to instruct a control unit to continue to perform the I/O operation in response to the control unit detecting that the data count does not match an amount of data required; receiving an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required; and responsive to receiving the IL value from the control unit, storing an IL indicator in a subchannel-status word.

公开(公告)号：AU2012278225B2

公开(公告)日：2015-08-13

申请号：AU2012278225

申请日：2012-04-11

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS WILLIAM ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS

IPC: G06F13/42

Abstract: A computer program product is provided for performing: sending, by a channel subsystem, a process login (PRLI) request message to the control unit that indicates whether the channel subsystem supports bi-directional data transfer; receiving a PRLI response message from the control unit that indicates whether the control unit supports bi-directional data transfer; gathering a plurality of commands, at least one which specifies an input data transfer and at least one specifying an output data transfer; sending at least one output data message to the control unit including output data to be transferred to the control unit, the output data message associated with the at least one of the plurality of commands specifying an output data transfer; and receiving at least one input message from the control unit including input data to be stored in a main storage of the host computer system.

公开(公告)号：GB2505140A

公开(公告)日：2014-02-19

申请号：GB201321837

申请日：2012-05-21

Applicant: IBM

Inventor： FLANAGAN JOHN ,  TURNER JEFFREY ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS ,  KUCH GEORGE PETER ,  HIGGS RAYMOND MICHAEL

IPC: G06F13/38

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

公开(公告)号：AU2012278225A1

公开(公告)日：2013-05-02

申请号：AU2012278225

申请日：2012-04-11

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS WILLIAM ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS

IPC: G06F13/42

Abstract: A computer program product is provided for performing: sending, by a channel subsystem, a process login (PRLI) request message to the control unit that indicates whether the channel subsystem supports bi-directional data transfer; receiving a PRLI response message from the control unit that indicates whether the control unit supports bi-directional data transfer; gathering a plurality of commands, at least one which specifies an input data transfer and at least one specifying an output data transfer; sending at least one output data message to the control unit including output data to be transferred to the control unit, the output data message associated with the at least one of the plurality of commands specifying an output data transfer; and receiving at least one input message from the control unit including input data to be stored in a main storage of the host computer system.

公开(公告)号：DE69522267T2

公开(公告)日：2002-06-13

申请号：DE69522267

申请日：1995-02-03

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033 ,  G06F13/40

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.