公开(公告)号：GB2595191A

公开(公告)日：2021-11-17

申请号：GB202112124

申请日：2020-01-27

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  REID COPELAND ,  PETRA LEBER ,  JONATHAN BRADBURY ,  SILVIA MELITTA MUELLER ,  XIN GUO

IPC: G06F9/455

Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

公开(公告)号：GB2572719A

公开(公告)日：2019-10-09

申请号：GB201909646

申请日：2017-11-30

Applicant: IBM

Inventor： SILVIA MELITTA MUELLER ,  PETRA LEBER ,  CEDRIC LICHTENAU

IPC: G06F7/499 ,  G06F7/505

Abstract: A circuit is provided which includes arithmetic computation logic (201) configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector (210) to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector (210) operates on the operands prior to the arithmetic computation logic (201) producing the result to determine, independent of the result produced by the arithmetic computation logic (201), whether the result fits within the specified result length l.

公开(公告)号：GB2530989A

公开(公告)日：2016-04-13

申请号：GB201417580

申请日：2014-10-06

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  SILVIA MELITTA MUELLER ,  PETRA LEBER ,  STEVEN R CARLOUGH ,  MICHAEL KROENER

IPC: G06F7/499 ,  G06F7/485 ,  G06F7/491

Abstract: Floating point arithmetic logic (10) for rounding the final result of an arithmetic operation on a first number (104) and a second number (106) both in either binary floating point format or decimal floating point format. Binary floating point format numbers are mapped S10 to a decimal floating point format, by padding bits (18) to form digits in order to share the same fields as in a decimal floating point format. A guard digit (28) of zero (58) of at least one of the first or second numbers is generated S12 by transforming the first and second numbers (108; 110) using a compressing function (30) such as a carry-save adder. A result (130) and result plus one (132) are calculated depending on the arithmetic operation a sum (66), a first difference (67) or a second difference (68) of the transformed numbers (112, 114). Injection values (24, 26) for rounding a final result (20) are generated in dependence on the first and second numbers being in a decimal or binary floating point format, a rounding mode and of the arithmetic operation. Injection carry values (16, 17) are generated based on the transformed first and second floating point numbers and the injection values. The final result is selected from the result, the result plus one and a least significant digit (60) based on the injection carry values and end around carry signals.

公开(公告)号：GB2595170A

公开(公告)日：2021-11-17

申请号：GB202111753

申请日：2020-01-23

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  JONATHAN BRADBURY ,  REID COPELAND ,  PETRA LEBER

IPC: G06F9/06

Abstract: In a technique for instruction interrupt suppression for an overflow condition, an instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per- instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

公开(公告)号：IL284709D0

公开(公告)日：2021-08-31

申请号：IL28470921

申请日：2021-07-08

Applicant: IBM ,  CEDRIC LICHTENAU ,  JONATHAN D BRADBURY ,  ERIC M SCHWARZ ,  RAZVAN PETER FIGULI ,  STEFAN PAYER

Inventor： CEDRIC LICHTENAU ,  JONATHAN D BRADBURY ,  ERIC M SCHWARZ ,  RAZVAN PETER FIGULI ,  STEFAN PAYER

IPC: G06F16/903 ,  G06F17/16 ,  G06F40/205

Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

公开(公告)号：GB2573685A

公开(公告)日：2019-11-13

申请号：GB201910346

申请日：2018-01-08

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  MICHAEL KLEIN ,  NICOL HOFMANN

IPC: G06F7/48

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.

公开(公告)号：GB2530989B

公开(公告)日：2016-08-17

申请号：GB201417580

申请日：2014-10-06

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  SILVIA MELITTA MUELLER ,  PETRA LEBER ,  STEVEN R CARLOUGH ,  MICHAEL KROENER

IPC: G06F7/499 ,  G06F7/485 ,  G06F7/491

公开(公告)号：GB2531770A

公开(公告)日：2016-05-04

申请号：GB201419282

申请日：2014-10-30

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  ANDREAS KOENIG ,  THOMAS PFLUEGER ,  WILLIAM E HALL ,  ELAINE R PALMER ,  PETER A SANDON

IPC: G06F21/62 ,  G06F11/07 ,  G06F11/14 ,  H04L29/06

Abstract: A public encryption key, associated with a private decryption key, is provided 102 to a security engine of a computer system. The security engine may be separate from the computer systems processor. An extraction key, not accessible outside the security engine, is generated 104. The extraction key is encrypted 106 with the public encryption key, thereby obtaining an encrypted extraction key. State information of the computer system is collected 108, encrypted 110 with the extraction key and stored 112, preferably at a remote storage system. Access is requested 114 by a server to the stored, encrypted, collected state information by requesting the extraction key. In response to the server receiving 116 the extraction key, the stored, encrypted, collected state information is decrypted 118 with the extraction key. Multiple sets of encrypted state information, each having its own extraction key, may be collected and stored, the information perhaps originating from multiple or multi-tenant computer systems. The computer system may be a virtual machine (VM) having an identifier, the collected state information perhaps referring to the hardware system underlying the VM and with each of multiple sets of information comprising information relating only to one VM identifier.