公开(公告)号：JP2000137612A

公开(公告)日：2000-05-16

申请号：JP9931799

申请日：1999-04-06

Applicant: IBM

Inventor： CHARLES F WEBB ,  WEN HEI LEE

IPC: G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/318 ,  G06F13/00

Abstract: PROBLEM TO BE SOLVED: To reduce the number of millicode instructions and the number of machine cycles by executing a pack decimal division instruction as an inner code instruction and maintaining control by an inner code. SOLUTION: A cache memory unit 12 logically contains a writable inner code array 13 where a continuous address can be designated and millimode routines which are frequently called are stored in the inner code array 13. Conversion fetch (TRFET) millicode instruction supports a TRT instruction and a special millicode instruction for pack binary division realizes the access, inspection, preparation and storage function of an operand by using hardware control and data flow logic, which are designed to support a simpler pack binary operation containing addition and generates a quotient number. They are executed as inner code instructions and control is maintained in an inner code.

公开(公告)号：JP2000137611A

公开(公告)日：2000-05-16

申请号：JP9929599

申请日：1999-04-06

Applicant: IBM

Inventor： CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To reduce the number of millicode instructions and the number of machine cycles by generating a necessary value through the use of information in a general-purpose register, a condition code and a millicode flag. SOLUTION: A cache memory unit 12 logically contains a writable inner code array 13 where a continuous address can be designated and millimode routines which are frequently called are stored in the inner code array 13. When a system enters a millimode millicode routine, one or plural conversion fetch (TPFET) millicode instruction supports a conversion/test (TRT) instruction. The TRFET instruction follows an ESA/390 architecture and generates the necessary value by using information in a general-purpose register, a condition code and a millicode flag. Thus, the general-purpose registers 1 of the processor and the condition code are updated.

公开(公告)号：JP2000112753A

公开(公告)日：2000-04-21

申请号：JP11053699

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain a method for operating a computer that has a milli-mode function by giving control, that enables a BHT operation to continue, to a milli-code except in the case of a specific situation where the control of an instruction fetch operation is needed. SOLUTION: A searching means 6 supplies a start address that is used when a branch history table(BHT) 5 accesses a BHT array 8 to the table (BHT) 5 which supplies information that gives an instruction to an instruction fetching means 2. Target information is latched in a register 10, and instruction address information is compared with a search address by a comparator 9. Results of the instruction address comparator 9 and a global disable latch 13 are used to decide if hit takes place and which set is desirable in hit detection logic 12. The selection of the set is used to control a multiplexer 11 and to make the instruction fetching means 2 gate correct branch target information.